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Searched refs:TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h10491 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x00000014 macro
Dgfx_7_2_sh_mask.h14002 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 macro
Dgfx_8_0_sh_mask.h15884 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 macro
Dgfx_8_1_sh_mask.h16464 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT 0x14 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h21977 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_9_4_3_sh_mask.h25471 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_9_1_sh_mask.h23284 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_9_2_1_sh_mask.h23286 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_9_4_2_sh_mask.h17103 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_11_5_0_sh_mask.h28345 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_11_0_0_sh_mask.h32500 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_12_0_0_sh_mask.h36412 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_11_0_3_sh_mask.h34998 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_10_1_0_sh_mask.h31909 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro
Dgc_10_3_0_sh_mask.h30335 #define TA_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT … macro