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Searched refs:TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h10483 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0x0000000a macro
Dgfx_7_2_sh_mask.h13990 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa macro
Dgfx_8_0_sh_mask.h15872 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa macro
Dgfx_8_1_sh_mask.h16452 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT 0xa macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h21956 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_9_4_3_sh_mask.h25451 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_9_1_sh_mask.h23263 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_9_2_1_sh_mask.h23266 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_9_4_2_sh_mask.h17083 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_11_5_0_sh_mask.h28325 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_11_0_0_sh_mask.h32480 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_12_0_0_sh_mask.h36392 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_11_0_3_sh_mask.h34978 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_10_1_0_sh_mask.h31889 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro
Dgc_10_3_0_sh_mask.h30315 #define TA_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT … macro