| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| D | InlineAsmLowering.cpp | 458 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); in lowerInlineAsm() local
459 assert(SrcRegs.size() == 1 && "Single register is expected here"); in lowerInlineAsm()
462 Register In = SrcRegs[0]; in lowerInlineAsm()
466 if (!buildAnyextOrCopy(In, SrcRegs[0], MIRBuilder)) in lowerInlineAsm()
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| D | CallLowering.cpp | 291 ArrayRef<Register> SrcRegs) { in mergeVectorRegsToResultRegs() argument
294 LLT PartLLT = MRI.getType(SrcRegs[0]); in mergeVectorRegsToResultRegs()
301 return B.buildConcatVectors(DstRegs[0], SrcRegs); in mergeVectorRegsToResultRegs()
310 DstRegs[0], B.buildMergeLikeInstr(LCMTy, SrcRegs)); in mergeVectorRegsToResultRegs()
314 assert(SrcRegs.size() == 1); in mergeVectorRegsToResultRegs()
315 UnmergeSrcReg = SrcRegs[0]; in mergeVectorRegsToResultRegs()
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| D | LegalizerHelper.cpp | 1174 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); in narrowScalar() local
1180 SrcRegs[i / 2]); in narrowScalar()
1189 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); in narrowScalar()
1323 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1329 SrcRegs.push_back(SrcReg); in narrowScalar()
1333 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); in narrowScalar()
1344 DstRegs.push_back(SrcRegs[i]); in narrowScalar()
1361 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) in narrowScalar()
1379 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalar() local
1381 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); in narrowScalar()
[all …]
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| D | IRTranslator.cpp | 1403 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
1409 DstRegs[i] = SrcRegs[Idx++]; in translateExtractValue()
1420 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
1428 DstRegs[i] = SrcRegs[i]; in translateInsertValue()
1590 SmallVector<Register, 3> SrcRegs; in translateMemFunc() local
1598 SrcRegs.push_back(SrcReg); in translateMemFunc()
1604 Register &SizeOpReg = SrcRegs[SrcRegs.size() - 1]; in translateMemFunc()
1609 for (Register SrcReg : SrcRegs) in translateMemFunc()
2983 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0)); in translateFreeze() local
2985 assert(DstRegs.size() == SrcRegs.size() && in translateFreeze()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 776 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI() argument
778 assert(!SrcRegs.empty() && "No sources to create a PHI instruction?"); in insertPHI()
780 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg); in insertPHI()
783 assert(SrcRegs[0].SubReg == 0 && "should not have subreg operand"); in insertPHI()
790 for (const RegSubRegPair &RegPair : SrcRegs) { in insertPHI()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1600 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1610 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_EVENT_CALL()
1611 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_EVENT_CALL()
1625 if (SrcRegs[I] != DestRegs[I]) in LowerPATCHABLE_EVENT_CALL()
1627 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_EVENT_CALL()
1698 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
1708 SrcRegs[I] = getX86SubSuperRegister(Op->getReg(), 64); in LowerPATCHABLE_TYPED_EVENT_CALL()
1709 if (SrcRegs[I] != DestRegs[I]) { in LowerPATCHABLE_TYPED_EVENT_CALL()
1730 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); in LowerPATCHABLE_TYPED_EVENT_CALL()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIFixSGPRCopies.cpp | 963 SmallSet<std::pair<Register, unsigned>, 4> SrcRegs; in needToBeConvertedToVALU() local
972 SrcRegs.insert(std::pair(SiblingCopy->getOperand(1).getReg(), in needToBeConvertedToVALU()
976 Info->SiblingPenalty = SrcRegs.size(); in needToBeConvertedToVALU()
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| D | AMDGPURegisterBankInfo.cpp | 1131 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingLoad() local
1133 if (SrcRegs.empty()) in applyMappingLoad()
1134 SrcRegs.push_back(MI.getOperand(1).getReg()); in applyMappingLoad()
1140 Register BasePtrReg = SrcRegs[0]; in applyMappingLoad()
2468 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
2469 if (SrcRegs.empty()) in applyMappingImpl()
2489 B.buildFreeze(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2491 auto Freeze = B.buildFreeze(S32, SrcRegs[0]); in applyMappingImpl()
2500 B.buildCopy(DstRegs[0], SrcRegs[0]); in applyMappingImpl()
2555 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
[all …]
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| D | AMDGPULegalizerInfo.cpp | 2386 SmallVector<Register, 8> SrcRegs; in legalizeInsertVectorElt() local
2388 SrcRegs.push_back(MRI.createGenericVirtualRegister(EltTy)); in legalizeInsertVectorElt()
2389 B.buildUnmerge(SrcRegs, Vec); in legalizeInsertVectorElt()
2391 SrcRegs[IdxVal] = MI.getOperand(2).getReg(); in legalizeInsertVectorElt()
2392 B.buildMergeLikeInstr(Dst, SrcRegs); in legalizeInsertVectorElt()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 299 SmallVector<Register, 8> SrcRegs(NumSrcs); in tryCombineTrunc()
301 SrcRegs[i] = SrcMerge->getSourceReg(i); in tryCombineTrunc()
303 Builder.buildMergeValues(DstReg, SrcRegs); in tryCombineTrunc()
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