| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | RegAllocBasic.cpp | 230 const LiveInterval &Spill = *Intfs[i]; in spillInterferences() local
233 if (!VRM->hasPhys(Spill.reg())) in spillInterferences()
238 Matrix->unassign(Spill); in spillInterferences()
241 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); in spillInterferences()
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| D | StackFrameLayoutAnalysisPass.cpp | 53 Spill, // a Spill slot enumerator
71 SlotTy = SlotType::Spill; in SlotData()
116 case SlotType::Spill: in getTypeString()
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| D | InlineSpiller.cpp | 148 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
150 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
1059 MachineBasicBlock::iterator Spill = std::next(MI); in insertSpill() local
1060 LIS.InsertMachineInstrRangeInMaps(Spill, MIS.end()); in insertSpill()
1061 for (const MachineInstr &MI : make_range(Spill, MIS.end())) in insertSpill()
1065 dumpMachineInstrRangeWithSlotIndex(Spill, MIS.end(), LIS, "spill")); in insertSpill()
1070 if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1) in insertSpill()
1071 HSpiller.addToMergeableSpills(*Spill, StackSlot, Original); in insertSpill()
1247 void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, in addToMergeableSpills() argument
1258 SlotIndex Idx = LIS.getInstructionIndex(Spill); in addToMergeableSpills()
[all …]
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| /openbsd/src/gnu/llvm/llvm/docs/ |
| D | AArch64SME.rst | 183 stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
184 stp d13, d12, [sp, #16] // 16-byte Folded Spill
185 stp d11, d10, [sp, #32] // 16-byte Folded Spill
186 stp d9, d8, [sp, #48] // 16-byte Folded Spill
187 str x30, [sp, #64] // 8-byte Folded Spill
188 str s0, [sp, #76] // 4-byte Folded Spill
192 str s0, [sp, #76] // 4-byte Folded Spill
333 stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
334 stp d13, d12, [sp, #16] // 16-byte Folded Spill
335 stp d11, d10, [sp, #32] // 16-byte Folded Spill
[all …]
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| D | AMDGPUUsage.rst | 14224 Spill Table
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIFrameLowering.cpp | 97 auto Spill = MFI->getPrologEpilogSGPRSpillToVGPRLanes(FI).front(); in getVGPRSpillLaneOrTempRegister()
99 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';); in getVGPRSpillLaneOrTempRegister()
260 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in saveToVGPRLane() local
262 assert(Spill.size() == NumSubRegs); in saveToVGPRLane()
268 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_WRITELANE_B32), Spill[I].VGPR) in saveToVGPRLane()
270 .addImm(Spill[I].Lane) in saveToVGPRLane()
271 .addReg(Spill[I].VGPR, RegState::Undef); in saveToVGPRLane()
305 ArrayRef<SIRegisterInfo::SpilledReg> Spill = in restoreFromVGPRLane() local
307 assert(Spill.size() == NumSubRegs); in restoreFromVGPRLane()
314 .addReg(Spill[I].VGPR) in restoreFromVGPRLane()
[all …]
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| D | SIMachineFunctionInfo.cpp | 423 auto &Spill = VGPRToAGPRSpills[FI]; in allocateVGPRSpillToAGPR() local
426 if (!Spill.Lanes.empty()) in allocateVGPRSpillToAGPR()
427 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
431 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister); in allocateVGPRSpillToAGPR()
439 Spill.FullyAllocated = true; in allocateVGPRSpillToAGPR()
467 Spill.FullyAllocated = false; in allocateVGPRSpillToAGPR()
474 Spill.Lanes[I] = *NextSpillReg++; in allocateVGPRSpillToAGPR()
477 return Spill.FullyAllocated; in allocateVGPRSpillToAGPR()
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| D | SIMachineFunctionInfo.h | 895 void setHasSpilledSGPRs(bool Spill = true) {
896 HasSpilledSGPRs = Spill;
903 void setHasSpilledVGPRs(bool Spill = true) {
904 HasSpilledVGPRs = Spill;
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| D | SIRegisterInfo.cpp | 1729 SpilledReg Spill = VGPRSpills[i]; in spillSGPR() local
1739 SB.TII.get(AMDGPU::V_WRITELANE_B32), Spill.VGPR) in spillSGPR()
1741 .addImm(Spill.Lane) in spillSGPR()
1742 .addReg(Spill.VGPR); in spillSGPR()
1843 SpilledReg Spill = VGPRSpills[i]; in restoreSGPR() local
1846 .addReg(Spill.VGPR) in restoreSGPR()
1847 .addImm(Spill.Lane); in restoreSGPR()
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| /openbsd/src/gnu/llvm/compiler-rt/lib/xray/ |
| D | xray_trampoline_powerpc64_asm.S | 8 # Spill r3-r10, f1-f13, and vsr34-vsr45, which are parameter registers.
149 # Spill r3-r4, f1-f8, and vsr34-vsr41, which are return registers.
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | FunctionLoweringInfo.h | 100 Spill, enumerator
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | StatepointLowering.cpp | 184 if (Record.type != RecordType::Spill) in findPreviousSpillSlot()
923 Record.type = RecordType::Spill; in LowerAsSTATEPOINT()
1247 if (Record.type == RecordType::Spill) { in visitGCRelocate()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64SMEInstrInfo.td | 114 // Spill + fill
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| D | AArch64SVEInstrInfo.td | 1519 // Fill/Spill
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| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/ |
| D | Target.td | 60 int SpillSize = SS; // Spill slot size in bits.
61 int SpillAlignment = SA; // Spill slot alignment in bits.
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| /openbsd/src/gnu/llvm/llvm/include/llvm/IR/ |
| D | IntrinsicsAArch64.td | 2625 // Spill + fill
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| /openbsd/src/sys/arch/sparc64/sparc64/ |
| D | locore.s | 524 ! Spill either 32-bit or 64-bit register window.
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