| /openbsd/src/gnu/llvm/compiler-rt/lib/builtins/ |
| D | int_div_impl.inc | 26 // 1 <= sr <= N - 1. Shifts do not trigger UB.
55 // 1 <= sr <= N - 1. Shifts do not trigger UB.
|
| /openbsd/src/gnu/gcc/gcc/config/alpha/ |
| D | ev6.md | 99 ; Shifts issue to upper units.
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/config/alpha/ |
| D | ev6.md | 94 ; Shifts issue to upper units.
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 1399 auto &Shifts = getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR}) in AMDGPULegalizerInfo() local
1403 Shifts.legalFor({{S16, S16}, {V2S16, V2S16}}) in AMDGPULegalizerInfo()
1406 Shifts.legalFor({{S16, S16}}); in AMDGPULegalizerInfo()
1409 Shifts.widenScalarIf( in AMDGPULegalizerInfo()
1418 Shifts.maxScalarIf(typeIs(0, S16), 1, S16); in AMDGPULegalizerInfo()
1419 Shifts.clampScalar(1, S32, S32); in AMDGPULegalizerInfo()
1420 Shifts.widenScalarToNextPow2(0, 16); in AMDGPULegalizerInfo()
1421 Shifts.clampScalar(0, S16, S64); in AMDGPULegalizerInfo()
1431 Shifts.clampScalar(1, S32, S32); in AMDGPULegalizerInfo()
1432 Shifts.widenScalarToNextPow2(0, 32); in AMDGPULegalizerInfo()
[all …]
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64SchedCyclone.td | 138 // Shifts and Bitfield Operations
176 // EXTR Shifts a pair of registers and requires two micro-ops.
473 // 7.9.4 Shifts and Bitfield Operations
|
| /openbsd/src/gnu/gcc/gcc/config/m32c/ |
| D | shift.md | 25 ; Shifts are unusual for m32c. We only support shifting in one
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/config/stormy16/ |
| D | stormy16.md | 487 ;; :: 16 bit Integer Shifts and Rotates
614 ;; :: 32 bit Integer Shifts and Rotates
|
| /openbsd/src/gnu/gcc/gcc/config/stormy16/ |
| D | stormy16.md | 525 ;; :: 16 bit Integer Shifts and Rotates
698 ;; :: 32 bit Integer Shifts and Rotates
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/ |
| D | CombinerHelper.cpp | 5132 SmallVector<Register, 16> Shifts, Factors; in buildSDivUsingMul() local
5140 Shifts.push_back(Shifts[0]); in buildSDivUsingMul()
5159 Shifts.push_back(MIB.buildConstant(ScalarShiftAmtTy, Shift).getReg(0)); in buildSDivUsingMul()
5171 Shift = MIB.buildBuildVector(ShiftAmtTy, Shifts).getReg(0); in buildSDivUsingMul()
5174 Shift = Shifts[0]; in buildSDivUsingMul()
|
| /openbsd/src/gnu/llvm/clang/include/clang/Basic/ |
| D | arm_neon.td | 395 // E.3.11 Shifts by signed variable
402 // E.3.12 Shifts by constant
420 // E.3.13 Shifts with insert
897 // Shifts by constant
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 5776 SmallVector<SDValue, 16> Shifts, Factors; in BuildExactSDIV() local
5792 Shifts.push_back(DAG.getConstant(Shift, dl, ShSVT)); in BuildExactSDIV()
5803 Shift = DAG.getBuildVector(ShVT, dl, Shifts); in BuildExactSDIV()
5806 assert(Shifts.size() == 1 && Factors.size() == 1 && in BuildExactSDIV()
5809 Shift = DAG.getSplatVector(ShVT, dl, Shifts[0]); in BuildExactSDIV()
5813 Shift = Shifts[0]; in BuildExactSDIV()
5889 SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks; in BuildSDIV() local
5916 Shifts.push_back(DAG.getConstant(magics.ShiftAmount, dl, ShSVT)); in BuildSDIV()
5932 Shift = DAG.getBuildVector(ShVT, dl, Shifts); in BuildSDIV()
5936 Shifts.size() == 1 && ShiftMasks.size() == 1 && in BuildSDIV()
[all …]
|
| D | SelectionDAG.cpp | 3155 unsigned Shifts = IsLE ? i : SubScale - 1 - i; in computeKnownBits() local
3156 Known.insertBits(Known2, SubBitWidth * Shifts); in computeKnownBits()
3175 unsigned Shifts = IsLE ? i : NumElts - 1 - i; in computeKnownBits() local
3176 unsigned Offset = (Shifts % SubScale) * BitWidth; in computeKnownBits()
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/config/sh/ |
| D | lib1funcs.asm | 217 ! r5: Shifts
368 ! r5: Shifts
527 ! r5: Shifts
|
| /openbsd/src/gnu/gcc/gcc/config/sh/ |
| D | lib1funcs.asm | 236 ! r5: Shifts
387 ! r5: Shifts
546 ! r5: Shifts
|
| /openbsd/src/gnu/gcc/gcc/config/mt/ |
| D | mt.md | 906 ;; 32 bit Integer Shifts and Rotates
|
| /openbsd/src/gnu/gcc/gcc/config/fr30/ |
| D | fr30.md | 843 ;;{{{ Shifts
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/config/fr30/ |
| D | fr30.md | 838 ;;{{{ Shifts
|
| /openbsd/src/gnu/gcc/gcc/config/arm/ |
| D | iwmmxt.md | 1114 ;; Shifts
|
| /openbsd/src/gnu/llvm/llvm/include/llvm/IR/ |
| D | IntrinsicsARM.td | 573 // Vector Shifts:
|
| D | IntrinsicsPowerPC.td | 1122 // Right Shifts.
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/config/d30v/ |
| D | d30v.md | 1551 ;; :: 32 bit Integer Shifts and Rotates
1647 ;; :: 64 bit Integer Shifts and Rotates
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZScheduleZ196.td | 458 // Shifts
|
| D | SystemZScheduleZEC12.td | 469 // Shifts
|
| /openbsd/src/gnu/gcc/gcc/config/ia64/ |
| D | ia64.md | 4532 ;; :: 32 bit Integer Shifts and Rotates
4672 ;; :: 64 bit Integer Shifts and Rotates
4784 ;; :: 128 bit Integer Shifts and Rotates
|
| /openbsd/src/gnu/gcc/gcc/config/mn10300/ |
| D | mn10300.md | 1277 ;; Shifts don't set the V flag, but bitwise operations clear
|