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Searched refs:SchedReads (Results 1 – 3 of 3) sorted by relevance

/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DCodeGenSchedule.h426 std::vector<CodeGenSchedRW> SchedReads; variable
512 assert(Idx < SchedReads.size() && "bad SchedRead index"); in getSchedRead()
513 assert(SchedReads[Idx].isValid() && "invalid SchedRead"); in getSchedRead()
514 return SchedReads[Idx]; in getSchedRead()
DCodeGenSchedule.cpp598 SchedReads.resize(1); in collectSchedRW()
675 SchedReads.emplace_back(SchedReads.size(), SRDef); in collectSchedRW()
700 } for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; in collectSchedRW()
703 SchedReads[RIdx].dump(); in collectSchedRW()
730 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
838 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findRWForSequence()
858 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in findOrInsertRW()
933 dbgs() << " " << SchedReads[Read].Name; in collectSchedClasses()
952 dbgs() << " " << SchedReads[RIdx].Name; in collectSchedClasses()
990 Name += SchedReads[Idx].Name; in createSchedClassName()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMScheduleR52.td45 // Cortex-R52 specific SchedReads