| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 270 SUBC, enumerator
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.h | 40 SUBC, // Sub with carry: (X, Y, Cin) -> (X+~Y+Cin, Cout). enumerator
|
| D | HexagonISelLowering.cpp | 1884 case HexagonISD::SUBC: return "HexagonISD::SUBC"; in getTargetNodeName()
3280 SDValue SubC = DAG.getNode(HexagonISD::SUBC, dl, Op.getNode()->getVTList(), in LowerAddSubCarry()
|
| D | HexagonISelDAGToDAG.cpp | 945 case HexagonISD::SUBC: return SelectAddSubCarry(N); in Select()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 111 SUBC, // Sub with carry enumerator
|
| D | ARMISelLowering.cpp | 1710 MAKE_CASE(ARMISD::SUBC) in getTargetNodeName()
4995 SDValue Carry = DAG.getNode(ARMISD::SUBC, DL, in ConvertBooleanCarryToCarryFlag()
5035 Value = DAG.getNode(ARMISD::SUBC, dl, VTs, LHS, RHS); in LowerUnsignedALUO()
12774 AddcSubcNode->getOpcode() != ARMISD::SUBC)) in AddCombineTo64bitMLAL()
12872 if (AddcSubcNode->getOpcode() == ARMISD::SUBC) { in AddCombineTo64bitMLAL()
12881 } else if (AddcSubcNode->getOpcode() == ARMISD::SUBC) in AddCombineTo64bitMLAL()
12986 if (N->getOpcode() == ARMISD::SUBC && N->hasAnyUseOfValue(1)) { in PerformAddcSubcCombine()
13004 unsigned Opcode = (N->getOpcode() == ARMISD::ADDC) ? ARMISD::SUBC in PerformAddcSubcCombine()
18678 case ARMISD::SUBC: return PerformAddcSubcCombine(N, DCI, Subtarget); in PerformDAGCombine()
19850 case ARMISD::SUBC: in computeKnownBitsForTargetNode()
|
| D | ARMISelDAGToDAG.cpp | 3983 N->getOperand(2).getOpcode() != ARMISD::SUBC || in Select()
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 318 case ISD::SUBC: return "subc"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 2510 case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break; in ExpandIntegerResult()
2961 ISD::ADDC : ISD::SUBC, in ExpandIntRes_ADDSUB()
2971 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUB()
3062 Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps); in ExpandIntRes_ADDSUBC()
|
| D | TargetLowering.cpp | 5025 if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) in SimplifySetCC() local
5029 DAG.getConstant(SUBC->getAPIntValue() - RHSC->getAPIntValue(), in SimplifySetCC()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/ARC/ |
| D | ARCISelLowering.cpp | 126 setOperationAction(ISD::SUBC, MVT::i32, Legal); in ARCTargetLowering()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1695 setOperationAction(ISD::SUBC, MVT::i32, Custom); in SparcTargetLowering()
1701 setOperationAction(ISD::SUBC, MVT::i64, Custom); in SparcTargetLowering()
3087 case ISD::SUBC: hiOpc = ISD::SUBE; break; in LowerADDC_ADDE_SUBC_SUBE()
3244 case ISD::SUBC: in LowerOperation()
|
| D | SparcInstrInfo.td | 796 defm SUBC : F3_12np <"subx", 0b001100>;
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 523 case ISD::SUBC: in Select()
825 ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC; in SelectADD_SUB_I64()
|
| D | R600ISelLowering.cpp | 188 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, in R600TargetLowering()
|
| D | AMDGPUISelLowering.cpp | 395 setOperationAction({ISD::ADDC, ISD::SUBC, ISD::ADDE, ISD::SUBE}, VT, Legal); in AMDGPUTargetLowering()
|
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 830 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, in initActions()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 549 defm SUBC : Arith<0b0111, "subc", sube, 0, [SR]>;
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 542 setOperationAction(ISD::SUBC, MVT::i32, Legal); in NVPTXTargetLowering()
547 setOperationAction(ISD::SUBC, MVT::i64, Legal); in NVPTXTargetLowering()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 73 setOperationAction(ISD::SUBC, VT, Legal); in AVRTargetLowering()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyISelLowering.cpp | 145 ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) { in WebAssemblyTargetLowering()
|
| /openbsd/src/gnu/llvm/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 415 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 239 setOperationAction(ISD::SUBC, VT, Legal); in PPCTargetLowering()
17353 SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue), in combineADDToADDZE()
|
| /openbsd/src/gnu/usr.bin/gcc/gcc/config/c4x/ |
| D | c4x.md | 36 ; ROLC, RORC, SIGI, STFI, STII, SUBC, SWI
|
| /openbsd/src/gnu/gcc/gcc/config/c4x/ |
| D | c4x.md | 36 ; ROLC, RORC, SIGI, STFI, STII, SUBC, SWI
|