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Searched refs:SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h9169 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x00000000 macro
Dgfx_7_2_sh_mask.h11866 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 macro
Dgfx_8_0_sh_mask.h13712 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 macro
Dgfx_8_1_sh_mask.h14110 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT 0x0 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h21649 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_4_3_sh_mask.h25118 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_1_sh_mask.h22956 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_2_1_sh_mask.h22923 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_9_4_2_sh_mask.h16738 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_11_5_0_sh_mask.h27776 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_11_0_0_sh_mask.h31927 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_12_0_0_sh_mask.h35938 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_11_0_3_sh_mask.h34425 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_10_1_0_sh_mask.h31594 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro
Dgc_10_3_0_sh_mask.h29962 #define SQ_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT … macro