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Searched refs:SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h13564 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 macro
Dgfx_8_1_sh_mask.h13962 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT 0x2 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h2169 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_9_4_3_sh_mask.h2178 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_9_1_sh_mask.h2017 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_9_2_1_sh_mask.h2040 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_9_4_2_sh_mask.h25461 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_11_0_0_sh_mask.h7045 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_12_0_0_sh_mask.h23745 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_11_0_3_sh_mask.h7902 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_10_1_0_sh_mask.h7721 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro
Dgc_10_3_0_sh_mask.h8056 #define SQ_DSM_CNTL__SPI_BACKPRESSURE_0__SHIFT … macro