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Searched refs:SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT (Results 1 – 12 of 12) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h13572 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa macro
Dgfx_8_1_sh_mask.h13970 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT 0xa macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h2173 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_9_4_3_sh_mask.h2182 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_9_1_sh_mask.h2021 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_9_2_1_sh_mask.h2044 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_9_4_2_sh_mask.h25465 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_11_0_0_sh_mask.h7049 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_12_0_0_sh_mask.h23749 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_11_0_3_sh_mask.h7906 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_10_1_0_sh_mask.h7725 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro
Dgc_10_3_0_sh_mask.h8060 #define SQ_DSM_CNTL__SGPR_ENABLE_SINGLE_WRITE__SHIFT … macro