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Searched refs:SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK (Results 1 – 14 of 14) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h8901 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf macro
Dgfx_8_0_sh_mask.h10521 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf macro
Dgfx_8_1_sh_mask.h10919 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK 0xf macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h12411 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_9_4_3_sh_mask.h15937 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_9_1_sh_mask.h13711 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_9_2_1_sh_mask.h13576 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_9_4_2_sh_mask.h25001 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_11_5_0_sh_mask.h22197 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_11_0_0_sh_mask.h26185 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_12_0_0_sh_mask.h33323 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_11_0_3_sh_mask.h28685 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_10_1_0_sh_mask.h19781 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro
Dgc_10_3_0_sh_mask.h18076 #define SPI_RESOURCE_RESERVE_CU_0__VGPR_MASK … macro