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Searched refs:SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h7670 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0x0000f000L macro
Dgfx_7_2_sh_mask.h9213 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 macro
Dgfx_8_0_sh_mask.h10933 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 macro
Dgfx_8_1_sh_mask.h11331 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK 0xf000 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h21643 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_9_4_3_sh_mask.h25112 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_9_1_sh_mask.h22950 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_9_2_1_sh_mask.h22917 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_9_4_2_sh_mask.h16732 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_11_5_0_sh_mask.h27690 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_11_0_0_sh_mask.h31841 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_12_0_0_sh_mask.h35852 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_11_0_3_sh_mask.h34339 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_10_1_0_sh_mask.h31588 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro
Dgc_10_3_0_sh_mask.h29956 #define SPI_PERFCOUNTER_BINS__BIN1_MAX_MASK … macro