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Searched refs:SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v9.c969 wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK; in get_wave_count()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h11085 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff macro
Dgfx_8_0_sh_mask.h12811 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff macro
Dgfx_8_1_sh_mask.h13209 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK 0x7ff macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h4454 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_9_4_3_sh_mask.h4778 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_9_1_sh_mask.h3932 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_9_2_1_sh_mask.h3838 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_9_4_2_sh_mask.h24771 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_11_5_0_sh_mask.h4561 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_11_0_0_sh_mask.h7458 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_12_0_0_sh_mask.h25029 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_11_0_3_sh_mask.h9005 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_10_1_0_sh_mask.h8702 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro
Dgc_10_3_0_sh_mask.h9013 #define SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK … macro