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Searched refs:SETULT (Results 1 – 25 of 51) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DISDOpcodes.h1442 SETULT, // 1 1 0 0 True if unordered or less than enumerator
1468 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DAnalysis.cpp201 case FCmpInst::FCMP_ULT: return ISD::SETULT; in getFCmpCondCode()
213 case ISD::SETOLT: case ISD::SETULT: return ISD::SETLT; in getFCmpCodeWithoutNaN()
230 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
254 case ISD::SETULT: in getICmpCondCode()
/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVE.h224 case ISD::SETULT: in intCondCode2Icc()
268 case ISD::SETULT: in fpCondCode2Fcc()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVISelDAGToDAG.h126 case ISD::SETULT: in getRISCVCCForIntCC()
DRISCVInstrInfoVSDPatterns.td684 defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
691 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSLTU", SETULT, SETUGT>;
695 defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
707 defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
DRISCVInstrInfoVVLPatterns.td1446 defm : VPatIntegerSetCCVL_VV_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
1453 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSLTU", SETULT, SETUGT>;
1457 defm : VPatIntegerSetCCVL_VX_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
1465 defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
1469 defm : VPatIntegerSetCCVL_VIPlus1_Swappable<vti, "PseudoVMSLEU", SETULT, SETUGT,
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp3319 case ISD::SETULT: { in get32BitZExtCompare()
3492 case ISD::SETULT: { in get32BitSExtCompare()
3648 case ISD::SETULT: { in get64BitZExtCompare()
3811 case ISD::SETULT: { in get64BitSExtCompare()
4076 case ISD::SETULT: in SelectCC()
4103 case ISD::SETULT: in SelectCC()
4164 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
4196 case ISD::SETULT: return 0; in getCRIdxForSetCC()
4218 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break; in getVCmpInst()
4226 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break; in getVCmpInst()
[all …]
DPPCInstrInfo.td3379 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETULT)),
3442 // SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
3622 def : Pat<(i1 (setcc i32:$s1, immZExt16:$imm, SETULT)),
3650 def : Pat<(i1 (setcc i32:$s1, i32:$s2, SETULT)),
3662 def : Pat<(i1 (setcc i64:$s1, immZExt16:$imm, SETULT)),
3690 def : Pat<(i1 (setcc i64:$s1, i64:$s2, SETULT)),
3885 def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETULT)),
3916 def : Pat<(i32 (selectcc i1:$lhs, i1:$rhs, i32:$tval, i32:$fval, SETULT)),
3937 def : Pat<(i64 (selectcc i1:$lhs, i1:$rhs, i64:$tval, i64:$fval, SETULT)),
3959 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
[all …]
DPPCInstrSPE.td840 def : Pat<(f32 (selectcc i1:$lhs, i1:$rhs, f32:$tval, f32:$fval, SETULT)),
861 def : Pat<(f64 (selectcc i1:$lhs, i1:$rhs, f64:$tval, f64:$fval, SETULT)),
/openbsd/src/gnu/llvm/llvm/lib/Target/BPF/
DBPFISelLowering.cpp580 case ISD::SETULT: in NegateCC()
792 SET_NEWCC(SETULT, JULT); in EmitInstrWithCustomInserter()
DBPFInstrInfo.td101 [{return (N->getZExtValue() == ISD::SETULT);}]>;
121 [{return (N->getZExtValue() == ISD::SETULT);}]>;
/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrInteger.td77 defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
DWebAssemblyISelLowering.cpp120 ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE}) in WebAssemblyTargetLowering()
249 for (auto CC : {ISD::SETUGT, ISD::SETUGE, ISD::SETULT, ISD::SETULE}) in WebAssemblyTargetLowering()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp377 case ISD::SETULT: in softenSetCCOperands()
3847 if (Cond == ISD::CondCode::SETULT) { in optimizeSetCCOfSignedTruncationCheck()
4044 if (Cond == ISD::SETULT || Cond == ISD::SETUGT) { in simplifySetCCWithCTPOP()
4050 if (C1.ugt(CostLimit + (Cond == ISD::SETULT))) in simplifySetCCWithCTPOP()
4052 if (C1 == 0 && (Cond == ISD::SETULT)) in simplifySetCCWithCTPOP()
4055 unsigned Passes = C1.getLimitedValue() - (Cond == ISD::SETULT); in simplifySetCCWithCTPOP()
4063 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in simplifySetCCWithCTPOP()
4458 case ISD::SETULT: in SimplifySetCC()
4481 case ISD::SETULT: in SimplifySetCC()
4685 ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; in SimplifySetCC()
[all …]
DLegalizeIntegerTypes.cpp2800 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
2870 return std::make_pair(ISD::SETULT, ISD::UMIN); in getExpandedMinMaxOps()
3018 ISD::SETULT); in ExpandIntRes_ADDSUB()
3033 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
3106 Cond = ISD::SETULT; in ExpandIntRes_UADDSUBO()
3988 SDValue HLULT = DAG.getSetCC(dl, BoolNVT, ResultHL, HLHiMask, ISD::SETULT); in ExpandIntRes_MULFIX()
4922 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
4994 case ISD::SETUGT: CCCode = ISD::SETULT; FlipOperands = true; break; in IntegerExpandSetCCOperands()
DSelectionDAGDumper.cpp463 case ISD::SETULT: return "setult"; in getOperationName()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARC/
DARCISelLowering.cpp48 case ISD::SETULT: in ISDCCtoARCCC()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp953 case ISD::SETULT: in isLegalDSPCondCode()
1758 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1764 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
1847 Op->getOperand(2), ISD::SETULT); in lowerINTRINSIC_WO_CHAIN()
DMipsMSAInstrInfo.td150 def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
151 def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
178 def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
179 def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
180 def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
181 def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
DMipsDSPInstrInfo.td1419 def : DSPSetCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
1432 def : DSPSelectCCPat<PseudoCMPU_LT_QB, PseudoPICK_QB, v4i8, SETULT>;
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonISelLoweringHVX.cpp265 setCondCodeAction(ISD::SETULT, T, Expand); in initializeHVXLowering()
350 setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand); in initializeHVXLowering()
363 setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand); in initializeHVXLowering()
2410 SDValue Ovf = DAG.getSetCC(dl, PredTy, Add, A, ISD::SETULT); in emitHvxAddWithOverflow()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DR600ISelLowering.cpp89 ISD::SETUGT, ISD::SETULT, ISD::SETULE}, in R600TargetLowering()
92 setCondCodeAction({ISD::SETLE, ISD::SETLT, ISD::SETULE, ISD::SETULT}, in R600TargetLowering()
DAMDGPUInstructions.td342 def COND_ULT : PatFrag<(ops), (OtherVT SETULT)>;
DSIWholeQuadMode.cpp839 case ISD::SETULT: in lowerKillF32()
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRISelLowering.cpp620 case ISD::SETULT: in intCCToAVRCC()
745 CC = ISD::SETULT; in getAVRCmp()

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