| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86TargetTransformInfo.cpp | 3114 { ISD::SETCC, MVT::v2i64, { 2, 5, 1, 2 } }, in getCmpSelInstrCost()
3125 { ISD::SETCC, MVT::v32i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3126 { ISD::SETCC, MVT::v16i16, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3127 { ISD::SETCC, MVT::v64i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3128 { ISD::SETCC, MVT::v32i8, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
3135 { ISD::SETCC, MVT::v8f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3136 { ISD::SETCC, MVT::v4f64, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3137 { ISD::SETCC, MVT::v16f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3138 { ISD::SETCC, MVT::v8f32, { 1, 4, 1, 1 } }, in getCmpSelInstrCost()
3140 { ISD::SETCC, MVT::v8i64, { 1, 1, 1, 1 } }, in getCmpSelInstrCost()
[all …]
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| D | X86ISelLowering.cpp | 456 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
464 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
586 setOperationAction(ISD::SETCC, VT, Action); in X86TargetLowering()
870 setOperationAction(ISD::SETCC, MVT::f128, Custom); in X86TargetLowering()
941 setOperationAction(ISD::SETCC, VT, Expand); in X86TargetLowering()
1077 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
1427 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
1633 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
1804 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
2001 setOperationAction(ISD::SETCC, VT, Custom); in X86TargetLowering()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/ |
| D | LanaiISelLowering.h | 41 SETCC, enumerator
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| D | LanaiISelLowering.cpp | 88 setOperationAction(ISD::SETCC, MVT::i32, Custom); in LanaiTargetLowering()
188 case ISD::SETCC: in LowerOperation()
980 return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag); in LowerSETCC()
1104 case LanaiISD::SETCC: in getTargetNodeName()
1494 case LanaiISD::SETCC: in computeKnownBitsForTargetNode()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 54 SETCC, enumerator
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| D | MSP430ISelLowering.cpp | 92 setOperationAction(ISD::SETCC, MVT::i8, Custom); in MSP430TargetLowering()
93 setOperationAction(ISD::SETCC, MVT::i16, Custom); in MSP430TargetLowering()
347 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
1383 case MSP430ISD::SETCC: return "MSP430ISD::SETCC"; in getTargetNodeName()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/VE/ |
| D | VVPNodes.def | 119 ADD_VVP_OP(VVP_SETCC, SETCC)
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| /openbsd/src/gnu/llvm/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 65 // Both of these match to FCmp / SETCC.
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 736 SETCC, enumerator
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 68 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break; in ScalarizeVectorResult()
480 if (Cond->getOpcode() == ISD::SETCC) { in ScalarizeVecRes_VSELECT()
588 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecRes_SETCC()
667 case ISD::SETCC: in ScalarizeVectorOperand()
812 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, in ScalarizeVecOp_VSETCC()
990 case ISD::SETCC: in SplitVectorResult()
1895 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_LOAD()
1970 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_VP_STRIDED_LOAD()
2050 if (Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_MLOAD()
2141 if (SplitSETCC && Ops.Mask.getOpcode() == ISD::SETCC) { in SplitVecRes_Gather()
[all …]
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| D | LegalizeVectorOps.cpp | 452 case ISD::SETCC: { in LegalizeOp()
757 DAG.getNode(ISD::SETCC, SDLoc(Node), CondVT, Node->getOperand(0), in Expand()
778 case ISD::SETCC: in Expand()
1547 LHS = DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), LHS, RHS, CC, in ExpandSETCC()
1710 Ops[i] = DAG.getNode(ISD::SETCC, dl, in UnrollVSETCC()
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| D | DAGCombiner.cpp | 914 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
1754 case ISD::SETCC: return visitSETCC(N); in visit()
2348 if (Z.getOperand(0).getOpcode() != ISD::SETCC || in foldAddSubBoolOfMaskedVal()
5153 if (N0.getOperand(0).getOpcode() != ISD::SETCC) in isSaturatingMinMax()
5625 TLI.isOperationLegal(ISD::SETCC, OpVT)))) in foldLogicOfSetCCs()
8742 case ISD::SETCC: in visitXOR()
9159 if (N01CV && N01CV->isConstant() && N00.getOpcode() == ISD::SETCC && in visitSHL()
10469 if (Cond.getOpcode() != ISD::SETCC || !Cond.hasOneUse() || in foldSelectOfConstantsUsingSra()
10501 if (Cond.getOpcode() != ISD::SETCC || !Cond->hasOneUse()) in shouldConvertSelectOfConstantsToMath()
10673 if (N0.getOpcode() != ISD::SETCC || !N0.hasOneUse()) in foldVSelectToSignBitSplatMask()
[all …]
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| D | LegalizeDAG.cpp | 1039 case ISD::SETCC: in LegalizeOp()
1048 : (Opc == ISD::SETCC || Opc == ISD::VP_SETCC) ? 2 in LegalizeOp()
3563 if (Tmp1.getOpcode() == ISD::SETCC) { in ExpandNode()
3622 if (Tmp2.getOpcode() == ISD::SETCC && in ExpandNode()
3645 case ISD::SETCC: in ExpandNode()
3736 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags()); in ExpandNode()
4486 Node->getOpcode() == ISD::SETCC || in PromoteNode()
4738 case ISD::SETCC: in PromoteNode()
4763 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), Tmp1, in PromoteNode()
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| D | LegalizeFloatTypes.cpp | 858 case ISD::SETCC: Res = SoftenFloatOp_SETCC(N); break; in SoftenFloatOperand()
1046 NewLHS = DAG.getNode(ISD::SETCC, SDLoc(N), N->getValueType(0), NewLHS, in SoftenFloatOp_SETCC()
1809 case ISD::SETCC: Res = ExpandFloatOp_SETCC(N); break; in ExpandFloatOperand()
2120 case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break; in PromoteFloatOperand()
2931 case ISD::SETCC: Res = SoftPromoteHalfOp_SETCC(N); break; in SoftPromoteHalfOperand()
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| D | LegalizeTypesGeneric.cpp | 525 else if (Cond.getOpcode() == ISD::SETCC) { in SplitRes_Select()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 103 {ISD::SHL, ISD::SRA, ISD::SRL, ISD::SETCC, ISD::VSELECT}); in MipsSETargetLowering()
125 setOperationAction(ISD::SETCC, MVT::f16, Promote); in MipsSETargetLowering()
240 setOperationAction(ISD::SETCC, MVT::i32, Legal); in MipsSETargetLowering()
244 setOperationAction(ISD::SETCC, MVT::f32, Legal); in MipsSETargetLowering()
249 setOperationAction(ISD::SETCC, MVT::f64, Legal); in MipsSETargetLowering()
287 setOperationAction(ISD::SETCC, MVT::i64, Legal); in MipsSETargetLowering()
355 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAIntType()
392 setOperationAction(ISD::SETCC, Ty, Legal); in addMSAFloatType()
1044 case ISD::SETCC: in PerformDAGCombine()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 304 setOperationAction(ISD::SETCC, T, Custom); in initializeHVXLowering()
375 setOperationAction(ISD::SETCC, BoolW, Custom); in initializeHVXLowering()
419 setOperationAction(ISD::SETCC, VecTy, Custom); in initializeHVXLowering()
433 setOperationAction(ISD::SETCC, BoolTy, Custom); in initializeHVXLowering()
3128 SDValue SetCC = DAG.getNode(ISD::SETCC, dl, ResTy, in WidenHvxSetCC()
3184 case ISD::SETCC: in LowerHvxOperation()
3225 case ISD::SETCC: in LowerHvxOperation()
3375 case ISD::SETCC: in LowerHvxOperationWrapper()
3441 case ISD::SETCC: in ReplaceHvxNodeResults()
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| D | HexagonISelLowering.cpp | 1515 setOperationAction(ISD::SETCC, MVT::i8, Custom); in HexagonTargetLowering()
1516 setOperationAction(ISD::SETCC, MVT::i16, Custom); in HexagonTargetLowering()
1517 setOperationAction(ISD::SETCC, MVT::v4i8, Custom); in HexagonTargetLowering()
1518 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
1747 setOperationAction(ISD::SETCC, MVT::v2i16, Custom); in HexagonTargetLowering()
3367 case ISD::SETCC: return LowerSETCC(Op, DAG); in LowerOperation()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.h | 384 SETCC, enumerator
|
| D | R600ISelLowering.cpp | 97 setOperationAction(ISD::SETCC, {MVT::v4i32, MVT::v2i32}, Expand); in R600TargetLowering()
109 setOperationAction(ISD::SETCC, {MVT::i32, MVT::f32}, Expand); in R600TargetLowering()
747 ISD::SETCC, in lowerFP_TO_UINT()
757 ISD::SETCC, in lowerFP_TO_SINT()
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| D | AMDGPUInstrInfo.td | 195 def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
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| D | SIISelLowering.cpp | 221 setOperationAction(ISD::SETCC, MVT::i1, Promote); in SITargetLowering()
222 setOperationAction(ISD::SETCC, {MVT::v2i1, MVT::v4i1}, Expand); in SITargetLowering()
223 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); in SITargetLowering()
761 ISD::SETCC, in SITargetLowering()
1670 if (VT == MVT::i1 && Op == ISD::SETCC) in isTypeDesirableForOp()
4950 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, DL, CCVT, LHS, RHS, in lowerICMPIntrinsic()
4980 SDValue SetCC = DAG.getNode(AMDGPUISD::SETCC, SL, CCVT, Src0, in lowerFCMPIntrinsic()
4993 if (Src.getOpcode() == ISD::SETCC) { in lowerBALLOTIntrinsic()
4995 return DAG.getNode(AMDGPUISD::SETCC, SL, VT, Src.getOperand(0), in lowerBALLOTIntrinsic()
5020 AMDGPUISD::SETCC, SL, VT, DAG.getZExtOrTrunc(Src, SL, MVT::i32), in lowerBALLOTIntrinsic()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AVR/ |
| D | AVRISelLowering.cpp | 113 setOperationAction(ISD::SETCC, MVT::i8, Custom); in AVRTargetLowering()
114 setOperationAction(ISD::SETCC, MVT::i16, Custom); in AVRTargetLowering()
115 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AVRTargetLowering()
116 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AVRTargetLowering()
962 case ISD::SETCC: in LowerOperation()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 412 setOperationAction(ISD::SETCC, MVT::i32, Custom); in AArch64TargetLowering()
413 setOperationAction(ISD::SETCC, MVT::i64, Custom); in AArch64TargetLowering()
414 setOperationAction(ISD::SETCC, MVT::f16, Custom); in AArch64TargetLowering()
415 setOperationAction(ISD::SETCC, MVT::f32, Custom); in AArch64TargetLowering()
416 setOperationAction(ISD::SETCC, MVT::f64, Custom); in AArch64TargetLowering()
480 setOperationAction(ISD::SETCC, MVT::f128, Custom); in AArch64TargetLowering()
663 {ISD::SETCC, ISD::SELECT_CC, in AArch64TargetLowering()
696 setOperationAction(ISD::SETCC, MVT::v4f16, Expand); in AArch64TargetLowering()
724 setOperationAction(ISD::SETCC, MVT::v8f16, Expand); in AArch64TargetLowering()
946 setTargetDAGCombine(ISD::SETCC); in AArch64TargetLowering()
[all …]
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1674 setOperationAction(ISD::SETCC, MVT::i32, Expand); in SparcTargetLowering()
1675 setOperationAction(ISD::SETCC, MVT::f32, Expand); in SparcTargetLowering()
1676 setOperationAction(ISD::SETCC, MVT::f64, Expand); in SparcTargetLowering()
1677 setOperationAction(ISD::SETCC, MVT::f128, Expand); in SparcTargetLowering()
1706 setOperationAction(ISD::SETCC, MVT::i64, Expand); in SparcTargetLowering()
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