Searched refs:SDMA_PKT_POLL_REGMEM_DW5_INTERVAL (Results 1 – 13 of 13) sorted by relevance
| /openbsd/src/sys/dev/pci/drm/amd/amdgpu/ |
| D | sdma_v2_4.c | 290 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_hdp_flush()
771 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_pipeline_sync()
798 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v2_4_ring_emit_vm_flush()
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| D | sdma_v3_0.c | 466 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_hdp_flush()
1044 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_pipeline_sync()
1071 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v3_0_ring_emit_vm_flush()
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| D | sdma_v7_0.c | 369 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v7_0_ring_emit_hdp_flush()
1208 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v7_0_ring_emit_pipeline_sync()
1249 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v7_0_ring_emit_reg_wait()
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| D | sdma_v6_0.c | 337 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_hdp_flush()
1185 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v6_0_ring_emit_pipeline_sync()
1245 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v6_0_ring_emit_reg_wait()
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| D | sdma_v5_2.c | 355 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_hdp_flush()
1166 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_2_ring_emit_pipeline_sync()
1206 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_2_ring_emit_reg_wait()
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| D | sdma_v5_0.c | 537 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_hdp_flush()
1316 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */ in sdma_v5_0_ring_emit_pipeline_sync()
1356 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); in sdma_v5_0_ring_emit_reg_wait()
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| D | tonga_sdma_pkt_open.h | 2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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| D | iceland_sdma_pkt_open.h | 2019 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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| D | vega10_sdma_pkt_open.h | 2511 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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| D | sdma_v4_4_2.c | 409 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_4_2_wait_reg_mem()
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| D | sdma_v4_0.c | 850 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(inv)); /* retry count, poll interval */ in sdma_v4_0_wait_reg_mem()
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| D | navi10_sdma_pkt_open.h | 3835 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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| D | sdma_v6_0_0_pkt_open.h | 4547 #define SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(x) (((x) & SDMA_PKT_POLL_REGMEM_DW5_interval_mask) << SDM… macro
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