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Searched refs:SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT (Results 1 – 3 of 3) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_0_0_sh_mask.h4101 #define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT … macro
Dgc_12_0_0_sh_mask.h4495 #define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT … macro
Dgc_11_0_3_sh_mask.h4217 #define SDMA1_QUEUE3_RB_CNTL__WPTR_POLL_ENABLE__SHIFT … macro