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Searched refs:SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK (Results 1 – 6 of 6) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v12_0.c3986 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; in gfx_v12_0_update_coarse_grain_clock_gating()
Dgfx_v11_0.c5281 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK; in gfx_v11_0_update_coarse_grain_clock_gating()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_sh_mask.h790 #define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK … macro
Dgc_11_0_0_sh_mask.h783 #define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK … macro
Dgc_12_0_0_sh_mask.h681 #define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK … macro
Dgc_11_0_3_sh_mask.h805 #define SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK … macro