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Searched refs:S32 (Results 1 – 18 of 18) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp437 const LLT S32 = LLT::scalar(32); in AMDGPULegalizerInfo() local
499 S32, S64 in AMDGPULegalizerInfo()
503 S32, S64, S16 in AMDGPULegalizerInfo()
507 S32, S64, S16, V2S16 in AMDGPULegalizerInfo()
510 const LLT MinScalarFPTy = ST.has16BitInsts() ? S16 : S32; in AMDGPULegalizerInfo()
513 getActionDefinitionsBuilder(G_BRCOND).legalFor({S1, S32}); in AMDGPULegalizerInfo()
518 .legalFor({S32, S64, V2S16, S16, V4S16, S1, S128, S256}) in AMDGPULegalizerInfo()
526 .clampMaxNumElements(0, S32, 16) in AMDGPULegalizerInfo()
533 .legalFor({S32, S16, V2S16}) in AMDGPULegalizerInfo()
538 .maxScalar(0, S32); in AMDGPULegalizerInfo()
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DAMDGPURegisterBankInfo.cpp127 const LLT S32 = LLT::scalar(32); in applyBank() local
129 assert(MRI.getType(DstReg) == S32); in applyBank()
135 auto True = B.buildConstant(S32, Opc == AMDGPU::G_SEXT ? -1 : 1); in applyBank()
136 auto False = B.buildConstant(S32, 0); in applyBank()
702 LLT S32 = LLT::scalar(32); in buildReadFirstLane() local
710 auto Unmerge = B.buildUnmerge(S32, Src); in buildReadFirstLane()
718 MRI.setType(DstPart, NumParts == 1 ? Ty : S32); in buildReadFirstLane()
1084 const LLT S32 = LLT::scalar(32); in applyMappingLoad() local
1087 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
1091 auto WideLoad = B.buildLoadFromOffset(S32, PtrReg, *MMO, 0); in applyMappingLoad()
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DAMDGPUPreLegalizerCombiner.cpp127 const LLT S32 = LLT::scalar(32); in applyClampI64ToI16() local
131 auto Unmerge = B.buildUnmerge(S32, Src); in applyClampI64ToI16()
142 auto MinBoundaryDst = B.buildConstant(S32, MinBoundary); in applyClampI64ToI16()
143 auto MaxBoundaryDst = B.buildConstant(S32, MaxBoundary); in applyClampI64ToI16()
145 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
148 AMDGPU::G_AMDGPU_SMED3, {S32}, in applyClampI64ToI16()
DAMDGPUPostLegalizerCombiner.cpp184 const LLT S32 = LLT::scalar(32); in applyUCharToFloat() local
190 if (SrcTy != S32) in applyUCharToFloat()
191 SrcReg = B.buildAnyExtOrTrunc(S32, SrcReg).getReg(0); in applyUCharToFloat()
193 if (Ty == S32) { in applyUCharToFloat()
197 auto Cvt0 = B.buildInstr(AMDGPU::G_AMDGPU_CVT_F32_UBYTE0, {S32}, in applyUCharToFloat()
282 const LLT S32 = LLT::scalar(32); in applyCvtF32UByteN() local
285 if (SrcTy != S32) { in applyCvtF32UByteN()
287 CvtSrc = B.buildAnyExt(S32, CvtSrc).getReg(0); in applyCvtF32UByteN()
DAMDGPUCallLowering.cpp74 LLT S32 = LLT::scalar(32); in assignValueToReg() local
75 if (Ty != S32) { in assignValueToReg()
80 ExtReg = MIRBuilder.buildPtrToInt(S32, ExtReg).getReg(0); in assignValueToReg()
82 ExtReg = MIRBuilder.buildBitcast(S32, ExtReg).getReg(0); in assignValueToReg()
196 const LLT S32 = LLT::scalar(32); in getStackAddress() local
223 auto OffsetReg = MIRBuilder.buildConstant(S32, Offset); in getStackAddress()
877 const LLT S32 = LLT::scalar(32); in passSpecialInputs() local
889 InputReg = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
893 InputReg = MIRBuilder.buildConstant(S32, 0).getReg(0); in passSpecialInputs()
899 Register Y = MRI.createGenericVirtualRegister(S32); in passSpecialInputs()
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DSIISelLowering.cpp1923 const LLT S32 = LLT::scalar(32); in allocateSpecialEntryInputVGPRs() local
1928 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32); in allocateSpecialEntryInputVGPRs()
1943 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32); in allocateSpecialEntryInputVGPRs()
1957 MRI.setType(MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass), S32); in allocateSpecialEntryInputVGPRs()
/openbsd/src/sys/crypto/
Dsha2.c123 #define S32(b,x) (((x) >> (b)) | ((x) << (32 - (b)))) macro
132 #define Sigma0_256(x) (S32(2, (x)) ^ S32(13, (x)) ^ S32(22, (x)))
133 #define Sigma1_256(x) (S32(6, (x)) ^ S32(11, (x)) ^ S32(25, (x)))
134 #define sigma0_256(x) (S32(7, (x)) ^ S32(18, (x)) ^ R(3 , (x)))
135 #define sigma1_256(x) (S32(17, (x)) ^ S32(19, (x)) ^ R(10, (x)))
/openbsd/src/sys/lib/libsa/
Dsha2.c157 #define S32(b,x) (((x) >> (b)) | ((x) << (32 - (b)))) macro
166 #define Sigma0_256(x) (S32(2, (x)) ^ S32(13, (x)) ^ S32(22, (x)))
167 #define Sigma1_256(x) (S32(6, (x)) ^ S32(11, (x)) ^ S32(25, (x)))
168 #define sigma0_256(x) (S32(7, (x)) ^ S32(18, (x)) ^ R(3 , (x)))
169 #define sigma1_256(x) (S32(17, (x)) ^ S32(19, (x)) ^ R(10, (x)))
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/MCTargetDesc/
DMipsABIFlagsSection.cpp25 case FpABIKind::S32: in getFpABIValue()
41 case FpABIKind::S32: in getFpABIString()
DMipsABIFlagsSection.h23 enum class FpABIKind { ANY, XX, S32, S64, SOFT }; enumerator
188 FpABI = FpABIKind::S32; in setFpAbiFromPredicates()
/openbsd/src/lib/libc/hash/
Dsha2.c156 #define S32(b,x) (((x) >> (b)) | ((x) << (32 - (b)))) macro
165 #define Sigma0_256(x) (S32(2, (x)) ^ S32(13, (x)) ^ S32(22, (x)))
166 #define Sigma1_256(x) (S32(6, (x)) ^ S32(11, (x)) ^ S32(25, (x)))
167 #define sigma0_256(x) (S32(7, (x)) ^ S32(18, (x)) ^ R(3 , (x)))
168 #define sigma1_256(x) (S32(17, (x)) ^ S32(19, (x)) ^ R(10, (x)))
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp6027 const LLT S32 = LLT::scalar(32); in lowerU64ToF32BitOps() local
6030 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); in lowerU64ToF32BitOps()
6042 auto Zero32 = MIRBuilder.buildConstant(S32, 0); in lowerU64ToF32BitOps()
6045 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); in lowerU64ToF32BitOps()
6047 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); in lowerU64ToF32BitOps()
6048 auto Sub = MIRBuilder.buildSub(S32, K, LZ); in lowerU64ToF32BitOps()
6051 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); in lowerU64ToF32BitOps()
6062 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); in lowerU64ToF32BitOps()
6063 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); in lowerU64ToF32BitOps()
6068 auto One = MIRBuilder.buildConstant(S32, 1); in lowerU64ToF32BitOps()
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/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp5648 const LLT S32 = LLT::scalar(32); in selectIntrinsicWithSideEffects() local
5686 else if (Ty == LLT::fixed_vector(2, S32)) in selectIntrinsicWithSideEffects()
5688 else if (Ty == LLT::fixed_vector(4, S32)) in selectIntrinsicWithSideEffects()
5710 else if (Ty == LLT::fixed_vector(2, S32)) in selectIntrinsicWithSideEffects()
5712 else if (Ty == LLT::fixed_vector(4, S32)) in selectIntrinsicWithSideEffects()
5737 else if (Ty == LLT::fixed_vector(2, S32)) in selectIntrinsicWithSideEffects()
5739 else if (Ty == LLT::fixed_vector(4, S32)) in selectIntrinsicWithSideEffects()
/openbsd/src/etc/
Dpf.os555 # S32:64:1:56:M*,N,N,S,N,N,?12:.:AMIGA:3.9 BB2 with Miami stack
576 # S32:64:0:68:M512,N,W0,N,N,T,N,N,?12:.:Nokia:IPSO w/Checkpoint NG FP3
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsInstrFPU.td103 // S32 - single precision in 16 32bit even fp registers
109 // Only S32 and D32 are supported right now.
DMipsScheduleP5600.td459 def : InstRW<[P5600WriteFPUL], (instregex "^FCMP_(S32|D32|D64)$")>;
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMInstrVFP.td1788 // S32 (U=0, sx=1) -> SL
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp8597 FpABI = MipsABIFlagsSection::FpABIKind::S32; in parseFpABIValue()