Searched refs:Rs2 (Results 1 – 3 of 3) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.td | 293 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
294 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
295 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
306 def R : InstRR<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI),
307 !strconcat(AsmStr, "$DDDI\t$Rs1, $Rs2, $Rd"),
308 [(set GPR:$Rd, (OpNode GPR:$Rs1, GPR:$Rs2))]>;
395 def : Pat<(LanaiSubbF GPR:$Rs1, GPR:$Rs2),
396 (SUBB_F_R GPR:$Rs1, GPR:$Rs2)>;
443 : InstRR<0b111, (outs GPR:$Rd), (ins GPR:$Rs1, GPR:$Rs2, pred:$DDDI), AsmStr,
448 def SHL_R : ShiftRR<"sh$DDDI\t$Rs1, $Rs2, $Rd",
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| D | LanaiInstrFormats.td | 112 // opcode Rd Rs1 Rs2 \ operation /
115 // `Rd <- Rs1 op Rs2' iff condition DDDI is true.
129 // determined by the contents of `Rs2' interpreted as a two's complement
132 // condition DDDI is true, Rs2 otherwise. All other `JJJJJ' combinations
152 bits<5> Rs2;
162 let Inst{15 - 11} = Rs2;
225 // opcode Rd Rs1 Rs2 \ operation /
234 // 1. `Rs1 + constant' is replaced with `Rs1 op Rs2', where `op' is
261 bits<5> Rs2;
275 let Inst{15 - 11} = Rs2;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 414 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs2() local
416 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); in decodeRVCInstrRdRs2()
424 unsigned Rs2 = fieldFromInstruction(Insn, 2, 5); in decodeRVCInstrRdRs1Rs2() local
427 DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder); in decodeRVCInstrRdRs1Rs2()
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