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Searched refs:RegInfo (Results 1 – 25 of 105) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/tools/llvm-exegesis/lib/
DRegisterAliasing.cpp14 BitVector getAliasedBits(const MCRegisterInfo &RegInfo, in getAliasedBits() argument
16 BitVector AliasedBits(RegInfo.getNumRegs()); in getAliasedBits()
19 for (auto Itr = RegAliasItr(PhysReg, &RegInfo, true); Itr.isValid(); in getAliasedBits()
27 RegisterAliasingTracker::RegisterAliasingTracker(const MCRegisterInfo &RegInfo) in RegisterAliasingTracker() argument
28 : SourceBits(RegInfo.getNumRegs()), AliasedBits(RegInfo.getNumRegs()), in RegisterAliasingTracker()
29 Origins(RegInfo.getNumRegs()) {} in RegisterAliasingTracker()
32 const MCRegisterInfo &RegInfo, const BitVector &ReservedReg, in RegisterAliasingTracker() argument
34 : RegisterAliasingTracker(RegInfo) { in RegisterAliasingTracker()
38 FillOriginAndAliasedBits(RegInfo, SourceBits); in RegisterAliasingTracker()
41 RegisterAliasingTracker::RegisterAliasingTracker(const MCRegisterInfo &RegInfo, in RegisterAliasingTracker() argument
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DRegisterAliasing.h28 BitVector getAliasedBits(const MCRegisterInfo &RegInfo,
43 RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
48 RegisterAliasingTracker(const MCRegisterInfo &RegInfo,
64 RegisterAliasingTracker(const MCRegisterInfo &RegInfo);
67 void FillOriginAndAliasedBits(const MCRegisterInfo &RegInfo,
78 RegisterAliasingTrackerCache(const MCRegisterInfo &RegInfo,
88 const MCRegisterInfo &regInfo() const { return RegInfo; } in regInfo()
97 const MCRegisterInfo &RegInfo;
114 std::string debugString(const MCRegisterInfo &RegInfo, const BitVector &Regs);
DLlvmState.cpp116 const MCRegisterInfo &RegInfo = getRegInfo(); in createRegNameToRegNoMapping() local
118 std::make_unique<DenseMap<StringRef, unsigned>>(RegInfo.getNumRegs()); in createRegNameToRegNoMapping()
121 for (unsigned I = 1, E = RegInfo.getNumRegs(); I < E; ++I) in createRegNameToRegNoMapping()
122 (*Map)[RegInfo.getName(I)] = I; in createRegNameToRegNoMapping()
123 assert(Map->size() == RegInfo.getNumRegs() && "Size prediction failed"); in createRegNameToRegNoMapping()
/openbsd/src/gnu/llvm/llvm/lib/MC/
DMCInst.cpp21 void MCOperand::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
27 if (RegInfo) in print()
28 OS << RegInfo->getName(getReg()); in print()
41 getInst()->print(OS, RegInfo); in print()
72 void MCInst::print(raw_ostream &OS, const MCRegisterInfo *RegInfo) const { in print()
76 getOperand(i).print(OS, RegInfo); in print()
83 const MCRegisterInfo *RegInfo) const { in dump_pretty()
85 dump_pretty(OS, InstName, Separator, RegInfo); in dump_pretty()
89 const MCRegisterInfo *RegInfo) const { in dump_pretty()
98 getOperand(i).print(OS, RegInfo); in dump_pretty()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEFrameLowering.cpp93 const MipsRegisterInfo &RegInfo; member in __anon2c3d41ed0111::ExpandPseudo
102 RegInfo(*Subtarget.getRegisterInfo()) {} in ExpandPseudo()
173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond()
177 TII.loadRegFromStack(MBB, I, VR, FI, RC, &RegInfo, 0); in expandLoadCCond()
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond()
194 TII.storeRegToStack(MBB, I, VR, true, FI, RC, &RegInfo, 0); in expandStoreCCond()
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC()
210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo); in expandLoadACC()
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
215 TII.loadRegFromStack(MBB, I, VR0, FI, RC, &RegInfo, 0); in expandLoadACC()
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DMipsSERegisterInfo.cpp156 const MipsRegisterInfo *RegInfo = in eliminateFI() local
183 else if (RegInfo->hasStackRealignment(MF)) { in eliminateFI()
224 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); in eliminateFI() local
225 Register Reg = RegInfo.createVirtualRegister(PtrRC); in eliminateFI()
DMips16ISelDAGToDAG.cpp72 MachineRegisterInfo &RegInfo = MF.getRegInfo(); in initGlobalBaseReg() local
78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
79 V1 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
80 V2 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
DMipsSEISelLowering.cpp3027 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitBPOSGE32() local
3058 Register VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3064 Register VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32()
3096 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitMSACBranchPseudo() local
3127 Register RD1 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3133 Register RD2 = RegInfo.createVirtualRegister(RC); in emitMSACBranchPseudo()
3163 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FW() local
3174 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass); in emitCOPY_FW()
3181 Register Wt = RegInfo.createVirtualRegister( in emitCOPY_FW()
3209 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); in emitCOPY_FD() local
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/openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/
DSparcFrameLowering.cpp94 const SparcRegisterInfo &RegInfo = in emitPrologue() local
100 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
102 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
151 unsigned regFP = RegInfo.getDwarfRegNum(SP::I6, true); in emitPrologue()
164 unsigned regInRA = RegInfo.getDwarfRegNum(SP::I7, true); in emitPrologue()
165 unsigned regOutRA = RegInfo.getDwarfRegNum(SP::O7, true); in emitPrologue()
256 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
260 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
269 const SparcRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in getFrameIndexReference() local
287 } else if (RegInfo->hasStackRealignment(MF)) { in getFrameIndexReference()
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/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86CallFrameOptimization.cpp114 const X86RegisterInfo &RegInfo,
242 const X86RegisterInfo &RegInfo = in runOnMachineFunction() local
244 SlotSize = RegInfo.getSlotSize(); in runOnMachineFunction()
281 const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) { in classifyInstruction() argument
341 if (RegInfo.regsOverlap(Reg, RegInfo.getStackRegister())) in classifyInstruction()
345 if (RegInfo.regsOverlap(Reg, U)) in classifyInstruction()
359 const X86RegisterInfo &RegInfo = in collectCallInfo() local
383 Register StackPtr = RegInfo.getStackRegister(); in collectCallInfo()
415 Classification = classifyInstruction(MBB, I, RegInfo, UsedRegs); in collectCallInfo()
DX86MachineFunctionInfo.cpp27 const X86RegisterInfo *RegInfo = static_cast<const X86RegisterInfo *>( in setRestoreBasePointer() local
29 unsigned SlotSize = RegInfo->getSlotSize(); in setRestoreBasePointer()
/openbsd/src/gnu/llvm/llvm/lib/Transforms/Instrumentation/
DControlHeightReduction.cpp133 struct RegInfo { struct
134 RegInfo() = default;
135 RegInfo(Region *RegionIn) : R(RegionIn) {} in RegInfo() function
148 CHRScope(RegInfo RI) : BranchInsertPoint(nullptr) { in CHRScope()
201 for (RegInfo &RI : RegInfos) in addSub()
218 RegInfos, [&Boundary](const RegInfo &RI) { return Boundary == RI.R; }); in split()
221 ArrayRef<RegInfo> TailRegInfos(BoundaryIt, RegInfos.end()); in split()
223 for (const RegInfo &RI : TailRegInfos) in split()
235 [&Parent](const RegInfo &RI) { return Parent == RI.R; }) && in split()
250 for (const RegInfo &RI : RegInfos) in contains()
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/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DThumb1FrameLowering.cpp119 const ThumbRegisterInfo *RegInfo = in eliminateCallFramePseudoInstr() local
137 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, -Amount); in eliminateCallFramePseudoInstr()
140 emitCallSPUpdate(MBB, I, TII, dl, *RegInfo, Amount); in eliminateCallFramePseudoInstr()
154 const ThumbRegisterInfo *RegInfo = in emitPrologue() local
169 Register FramePtr = RegInfo->getFrameRegister(MF); in emitPrologue()
170 Register BasePtr = RegInfo->getBaseRegister(); in emitPrologue()
183 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -ArgRegsSaveSize, in emitPrologue()
195 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, in emitPrologue()
430 emitPrologueEpilogueSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes, in emitPrologue()
450 if (RegInfo->hasStackRealignment(MF)) { in emitPrologue()
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DARMFrameLowering.cpp203 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
211 return (RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
300 const ARMBaseRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in insertSEH() local
364 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in insertSEH()
378 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in insertSEH()
397 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg()); in insertSEH()
442 unsigned Reg = RegInfo->getSEHRegNum(MO.getReg()); in insertSEH()
473 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg()); in insertSEH()
479 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in insertSEH()
741 const ARMBaseRegisterInfo *RegInfo = STI.getRegisterInfo(); in emitPrologue() local
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/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVEFrameLowering.cpp314 const VERegisterInfo &RegInfo = *STI.getRegisterInfo(); in emitPrologue() local
316 bool NeedsStackRealignment = RegInfo.shouldRealignStack(MF); in emitPrologue()
322 if (NeedsStackRealignment && !RegInfo.canRealignStack(MF)) in emitPrologue()
422 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
426 RegInfo->hasStackRealignment(MF) || MFI.hasVarSizedObjects() || in hasFP()
448 const VERegisterInfo *RegInfo = STI.getRegisterInfo(); in getFrameIndexReference() local
459 if (RegInfo->hasStackRealignment(MF) && !isFixed) { in getFrameIndexReference()
470 FrameReg = RegInfo->getFrameRegister(MF); in getFrameIndexReference()
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DDetectDeadLanes.cpp99 const VRegInfo &RegInfo) const;
294 VRegInfo &RegInfo = VRegInfos[DefRegIdx]; in transferDefinedLanesStep() local
295 LaneBitmask PrevDefinedLanes = RegInfo.DefinedLanes; in transferDefinedLanesStep()
300 RegInfo.DefinedLanes = PrevDefinedLanes | DefinedLanes; in transferDefinedLanesStep()
453 const VRegInfo &RegInfo) const { in isUndefRegAtInput()
456 return (RegInfo.DefinedLanes & RegInfo.UsedLanes & Mask).none(); in isUndefRegAtInput()
540 const VRegInfo &RegInfo = VRegInfos[RegIdx]; in runOnce() local
541 if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) { in runOnce()
549 if (isUndefRegAtInput(MO, RegInfo)) { in runOnce()
DMachineSSAContext.cpp28 RegInfo = &MF->getRegInfo(); in setFunction()
56 return RegInfo->getVRegDef(value)->getParent(); in getDefBlock()
74 auto *MRI = RegInfo; in print()
DTargetRegisterInfo.cpp175 Printable printRegClassOrBank(Register Reg, const MachineRegisterInfo &RegInfo, in printRegClassOrBank() argument
177 return Printable([Reg, &RegInfo, TRI](raw_ostream &OS) { in printRegClassOrBank()
178 if (RegInfo.getRegClassOrNull(Reg)) in printRegClassOrBank()
179 OS << StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower(); in printRegClassOrBank()
180 else if (RegInfo.getRegBankOrNull(Reg)) in printRegClassOrBank()
181 OS << StringRef(RegInfo.getRegBankOrNull(Reg)->getName()).lower(); in printRegClassOrBank()
184 assert((RegInfo.def_empty(Reg) || RegInfo.getType(Reg).isValid()) && in printRegClassOrBank()
DTargetFrameLoweringImpl.cpp149 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in allocateScavengingFrameIndexesNearIncomingSP() local
150 return RegInfo->useFPForScavengingIndex(MF) && in allocateScavengingFrameIndexesNearIncomingSP()
151 !RegInfo->hasStackRealignment(MF); in allocateScavengingFrameIndexesNearIncomingSP()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp329 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in homogeneousPrologEpilog() local
330 if (MFI.hasVarSizedObjects() || RegInfo->hasStackRealignment(MF)) in homogeneousPrologEpilog()
430 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() local
441 RegInfo->hasStackRealignment(MF)) in hasFP()
857 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in canUseAsPrologue() local
860 if (!RegInfo->hasStackRealignment(*MF)) in canUseAsPrologue()
892 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in shouldCombineCSRLocalStackBump() local
919 if (RegInfo->hasStackRealignment(MF)) in shouldCombineCSRLocalStackBump()
982 const AArch64RegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in InsertSEH() local
991 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg()); in InsertSEH()
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/openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.h26 const NVPTXRegisterInfo RegInfo; variable
31 const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } in getRegisterInfo()
DNVPTXInstrInfo.cpp30 NVPTXInstrInfo::NVPTXInstrInfo() : RegInfo() {} in NVPTXInstrInfo()
40 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC)) in copyPhysReg()
/openbsd/src/gnu/llvm/llvm/include/llvm/MC/
DMCInst.h176 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
228 void print(raw_ostream &OS, const MCRegisterInfo *RegInfo = nullptr) const;
236 const MCRegisterInfo *RegInfo = nullptr) const;
238 const MCRegisterInfo *RegInfo = nullptr) const;
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp313 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in determineFrameLayout() local
315 unsigned LR = RegInfo->getRARegister(); in determineFrameLayout()
321 !RegInfo->hasBasePointer(MF); // No special alignment. in determineFrameLayout()
391 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in replaceFPWithRealFP() local
392 bool HasBP = RegInfo->hasBasePointer(MF); in replaceFPWithRealFP()
393 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg; in replaceFPWithRealFP()
486 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in findScratchRegister() local
487 const MCPhysReg *CSRegs = RegInfo->getCalleeSavedRegs(MBB->getParent()); in findScratchRegister()
534 const PPCRegisterInfo *RegInfo = Subtarget.getRegisterInfo(); in twoUniqueScratchRegsRequired() local
536 bool HasBP = RegInfo->hasBasePointer(MF); in twoUniqueScratchRegsRequired()
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/openbsd/src/gnu/llvm/lldb/source/Plugins/Process/Utility/
DRegisterContextPOSIX_s390x.h45 struct RegInfo { struct
55 RegInfo m_reg_info; argument

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