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Searched refs:RegIdx (Results 1 – 19 of 19) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DDetectDeadLanes.cpp106 void PutInWorklist(unsigned RegIdx) { in PutInWorklist() argument
107 if (WorklistMembers.test(RegIdx)) in PutInWorklist()
109 WorklistMembers.set(RegIdx); in PutInWorklist()
110 Worklist.push_back(RegIdx); in PutInWorklist()
357 unsigned RegIdx = Register::virtReg2Index(Reg); in determineInitialDefinedLanes() local
358 DefinedByCopy.set(RegIdx); in determineInitialDefinedLanes()
359 PutInWorklist(RegIdx); in determineInitialDefinedLanes()
490 for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) { in runOnce() local
491 Register Reg = Register::index2VirtReg(RegIdx); in runOnce()
494 VRegInfo &Info = VRegInfos[RegIdx]; in runOnce()
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DSplitKit.cpp461 VNInfo *SplitEditor::defValue(unsigned RegIdx, in defValue() argument
468 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defValue()
477 Values.insert(std::make_pair(std::make_pair(RegIdx, ParentVNI->id), FP)); in defValue()
498 void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) { in forceRecompute() argument
499 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI.id)]; in forceRecompute()
511 addDeadDef(LIS.getInterval(Edit->get(RegIdx)), VNI, false); in forceRecompute()
538 MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) { in buildCopy() argument
551 LiveInterval &DestLI = LIS.getInterval(Edit->get(RegIdx)); in buildCopy()
581 VNInfo *SplitEditor::defFromParent(unsigned RegIdx, const VNInfo *ParentVNI, in defFromParent() argument
585 LiveInterval *LI = &LIS.getInterval(Edit->get(RegIdx)); in defFromParent()
[all …]
DSplitKit.h343 LiveIntervalCalc &getLICalc(unsigned RegIdx) { in getLICalc() argument
344 return LICalc[SpillMode != SM_Partition && RegIdx != 0]; in getLICalc()
363 VNInfo *defValue(unsigned RegIdx, const VNInfo *ParentVNI, SlotIndex Idx,
370 void forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI);
378 VNInfo *defFromParent(unsigned RegIdx, const VNInfo *ParentVNI,
428 bool Late, unsigned RegIdx);
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMCallingConv.cpp201 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
206 while (RegIdx % RegAlign != 0 && RegIdx < RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
207 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
247 unsigned RegIdx = State.getFirstUnallocated(RegList); in CC_ARM_AAPCS_Custom_Aggregate() local
249 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
252 It.convertToReg(State.AllocateReg(RegList[RegIdx++])); in CC_ARM_AAPCS_Custom_Aggregate()
DARMISelLowering.cpp4510 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs); in LowerFormalArguments() local
4511 if (RegIdx != std::size(GPRArgRegs)) in LowerFormalArguments()
4512 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]); in LowerFormalArguments()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp887 struct RegIdxOp RegIdx; member
902 Op->RegIdx.Index = Index; in CreateReg()
903 Op->RegIdx.RegInfo = RegInfo; in CreateReg()
904 Op->RegIdx.Kind = RegKind; in CreateReg()
905 Op->RegIdx.Tok.Data = Str.data(); in CreateReg()
906 Op->RegIdx.Tok.Length = Str.size(); in CreateReg()
916 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPR32Reg()
917 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc); in getGPR32Reg()
919 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index); in getGPR32Reg()
925 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!"); in getGPRMM16Reg()
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/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRAsmPrinter.cpp130 unsigned RegIdx = ByteNumber / BytesPerReg; in PrintAsmOperand() local
131 if (RegIdx >= NumOpRegs) in PrintAsmOperand()
133 Reg = MI->getOperand(OpNum + RegIdx).getReg(); in PrintAsmOperand()
DAVRISelLowering.cpp1220 unsigned RegIdx = RegLastIdx + TotalBytes; in analyzeArguments() local
1221 RegLastIdx = RegIdx; in analyzeArguments()
1223 if (RegIdx >= RegList8.size()) { in analyzeArguments()
1238 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeArguments()
1240 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeArguments()
1249 RegIdx -= VT.getStoreSize(); in analyzeArguments()
1303 int RegIdx = TotalBytes - 1; in analyzeReturnValues() local
1308 Reg = CCInfo.AllocateReg(RegList8[RegIdx]); in analyzeReturnValues()
1310 Reg = CCInfo.AllocateReg(RegList16[RegIdx]); in analyzeReturnValues()
1317 RegIdx -= VT.getStoreSize(); in analyzeReturnValues()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64CollectLOH.cpp551 int RegIdx = mapRegToGPRIndex(LI.PhysReg); in runOnMachineFunction() local
552 if (RegIdx >= 0) in runOnMachineFunction()
553 LOHInfos[RegIdx].OneUser = true; in runOnMachineFunction()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.cpp78 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const { in getMSACtrlReg()
79 uint64_t RegNum = cast<ConstantSDNode>(RegIdx)->getZExtValue(); in getMSACtrlReg()
844 SDValue RegIdx = Node->getOperand(2); in trySelect() local
846 getMSACtrlReg(RegIdx), MVT::i32); in trySelect()
914 SDValue RegIdx = Node->getOperand(2); in trySelect() local
917 getMSACtrlReg(RegIdx), Value); in trySelect()
DMipsSEISelDAGToDAG.h35 unsigned getMSACtrlReg(const SDValue RegIdx) const;
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86ExpandPseudo.cpp668 for (int64_t OpndIdx = 7, RegIdx = 0; in ExpandVastartSaveXmmRegs() local
670 OpndIdx++, RegIdx++) { in ExpandVastartSaveXmmRegs()
674 NewMI.addImm(FrameOffset + VarArgsRegsOffset + RegIdx * 16); in ExpandVastartSaveXmmRegs()
DX86SpeculativeLoadHardening.cpp1873 unsigned RegIdx = Log2_32(RegBytes); in canHardenRegister() local
1874 assert(RegIdx < 4 && "Unsupported register size"); in canHardenRegister()
1886 if (RC == NOREXRegClasses[RegIdx]) in canHardenRegister()
1892 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]); in canHardenRegister()
DX86FastISel.cpp2632 unsigned RegIdx = X86::sub_16bit; in fastLowerIntrinsicCall() local
2633 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, RegIdx); in fastLowerIntrinsicCall()
DX86ISelLowering.cpp37212 for (unsigned RegIdx = 0; SavedRegs[RegIdx]; ++RegIdx) { in EmitSjLjDispatchBlock() local
37213 unsigned Reg = SavedRegs[RegIdx]; in EmitSjLjDispatchBlock()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2647 unsigned RegIdx = RegNum / AlignSize; in getRegularReg() local
2656 if (RegIdx >= RC.getNumRegs()) { in getRegularReg()
2661 return RC.getRegister(RegIdx); in getRegularReg()
4487 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS() local
4488 if (RegIdx & 1) { in validateGWS()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp6887 unsigned RegIdx = 3; in shouldOmitPredicateOperand() local
6895 RegIdx = 4; in shouldOmitPredicateOperand()
6897 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() && in shouldOmitPredicateOperand()
6899 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) || in shouldOmitPredicateOperand()
6901 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()))) in shouldOmitPredicateOperand()
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp1975 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgVGPRs); in allocateVGPR32Input() local
1976 if (RegIdx == ArgVGPRs.size()) { in allocateVGPR32Input()
1983 unsigned Reg = ArgVGPRs[RegIdx]; in allocateVGPR32Input()
1997 unsigned RegIdx = CCInfo.getFirstUnallocated(ArgSGPRs); in allocateSGPR32InputImpl() local
1998 if (RegIdx == ArgSGPRs.size()) in allocateSGPR32InputImpl()
2001 unsigned Reg = ArgSGPRs[RegIdx]; in allocateSGPR32InputImpl()
/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp12061 unsigned RegIdx = State.getFirstUnallocated(ArgGPRs); in CC_RISCV() local
12063 if (RegIdx != std::size(ArgGPRs) && RegIdx % 2 == 1) in CC_RISCV()