| /openbsd/src/gnu/usr.bin/binutils-2.17/include/opcode/ |
| D | i386.h | 95 { "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
112 { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
114 { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
117 { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
125 {"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
126 {"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} },
127 {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
130 {"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} },
131 {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
143 {"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
[all …]
|
| D | ChangeLog-9103 | 414 * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
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| /openbsd/src/gnu/usr.bin/binutils/include/opcode/ |
| D | i386.h | 93 { "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
106 { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} },
108 { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} },
111 { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } },
119 {"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
120 {"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} },
121 {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
125 {"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} },
126 {"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} },
127 {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} },
[all …]
|
| D | ChangeLog-9103 | 395 * i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
|
| /openbsd/src/gnu/usr.bin/binutils/gas/config/ |
| D | tc-i386.h | 266 #define Reg64 0x8 /* 64 bit reg */ macro
311 #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
312 #define WordReg (Reg16|Reg32|Reg64)
|
| D | tc-i386.c | 1118 { Reg64, "r64" },
1846 else if (i.types[op] & Reg64) in optimize_imm()
2216 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : in process_suffix()
2416 else if ((i.types[op] & Reg64) != 0 in check_long_reg()
3968 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
4857 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0
|
| /openbsd/src/gnu/usr.bin/binutils-2.17/gas/config/ |
| D | tc-i386.h | 256 #define Reg64 0x8 /* 64 bit reg */ macro
301 #define Reg (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
302 #define WordReg (Reg16|Reg32|Reg64)
|
| D | tc-i386.c | 1147 { Reg64, "r64" },
2032 else if (i.types[op] & Reg64) in optimize_imm()
2443 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : in process_suffix()
2697 else if ((i.types[op] & Reg64) != 0 in check_long_reg()
4381 RegXX = i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32;
4395 unsigned RegXX = (i.prefix[ADDR_PREFIX] == 0 ? Reg64 : Reg32);
5307 && ((r->reg_flags & (RegRex64 | RegRex)) | (r->reg_type & Reg64)) != 0 in parse_real_register()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 219 const Register Reg64 = MI->getOperand(0).getReg(); in expandLoadStackGuard() local
220 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32); in expandLoadStackGuard()
228 .addReg(Reg64, RegState::ImplicitDefine); in expandLoadStackGuard()
231 BuildMI(*MBB, MI, MI->getDebugLoc(), get(SystemZ::SLLG), Reg64) in expandLoadStackGuard()
232 .addReg(Reg64) in expandLoadStackGuard()
242 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0); in expandLoadStackGuard()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 552 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
560 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
578 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
584 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
590 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
596 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
|
| D | AArch64FastISel.cpp | 1883 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in emitLoad() local
1885 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emitLoad()
1889 ResultReg = Reg64; in emitLoad()
3978 Register Reg64 = MRI.createVirtualRegister(&AArch64::GPR64RegClass); in emiti1Ext() local
3980 TII.get(AArch64::SUBREG_TO_REG), Reg64) in emiti1Ext()
3984 ResultReg = Reg64; in emiti1Ext()
4498 Register Reg64 = createResultReg(&AArch64::GPR64RegClass); in optimizeIntExtLoad() local
4500 TII.get(AArch64::SUBREG_TO_REG), Reg64) in optimizeIntExtLoad()
4504 Reg = Reg64; in optimizeIntExtLoad()
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| /openbsd/src/gnu/usr.bin/binutils-2.17/gas/ |
| D | ChangeLog-2004 | 1472 (parse_register): Disallow Reg64 registers in 32-bit mode.
|
| D | ChangeLog-0001 | 3749 (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
3754 (Reg, WordReg): Add Reg64.
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| /openbsd/src/gnu/usr.bin/binutils/gas/ |
| D | ChangeLog-0001 | 3749 (Reg64, Imm32S, Imm64, Disp32S, Disp64): New macros.
3754 (Reg, WordReg): Add Reg64.
|