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Searched refs:RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK (Results 1 – 4 of 4) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_11_5_0_sh_mask.h35208 #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK … macro
Dgc_11_0_0_sh_mask.h40279 #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK … macro
Dgc_12_0_0_sh_mask.h39008 #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK … macro
Dgc_11_0_3_sh_mask.h43317 #define RTAVFS_REG20__RTAVFSZONE0CPOAVGDIV5_MASK … macro