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Searched refs:RLC_SAFE_MODE__CMD_MASK (Results 1 – 19 of 19) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dgfx_v9_4_3.c1387 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v9_4_3_xcc_set_safe_mode()
1404 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v9_4_3_xcc_unset_safe_mode()
Dgfx_v12_0.c3755 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v12_0_set_safe_mode()
3772 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v12_0_unset_safe_mode()
Dgfx_v8_0.c5546 data |= RLC_SAFE_MODE__CMD_MASK; in gfx_v8_0_set_safe_mode()
5574 data |= RLC_SAFE_MODE__CMD_MASK; in gfx_v8_0_unset_safe_mode()
Dgfx_v9_0.c4870 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v9_0_set_safe_mode()
4886 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v9_0_unset_safe_mode()
Dgfx_v11_0.c5054 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v11_0_set_safe_mode()
5070 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); in gfx_v11_0_unset_safe_mode()
Dgfx_v10_0.c7759 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v10_0_set_safe_mode()
7799 data = RLC_SAFE_MODE__CMD_MASK; in gfx_v10_0_unset_safe_mode()
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_8_0_sh_mask.h8529 #define RLC_SAFE_MODE__CMD_MASK 0x1 macro
Dgfx_8_1_sh_mask.h9085 #define RLC_SAFE_MODE__CMD_MASK 0x1 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h22763 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_9_4_3_sh_mask.h26312 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_9_1_sh_mask.h24050 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_9_2_1_sh_mask.h24053 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_9_4_2_sh_mask.h21527 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_11_5_0_sh_mask.h31583 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_11_0_0_sh_mask.h36857 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_12_0_0_sh_mask.h22405 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_11_0_3_sh_mask.h40229 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_10_1_0_sh_mask.h33233 #define RLC_SAFE_MODE__CMD_MASK … macro
Dgc_10_3_0_sh_mask.h33002 #define RLC_SAFE_MODE__CMD_MASK … macro