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Searched refs:RLC_MEM_SLP_CNTL__RESERVED1__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h7195 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018 macro
Dgfx_7_2_sh_mask.h7740 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 macro
Dgfx_8_0_sh_mask.h8556 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 macro
Dgfx_8_1_sh_mask.h9108 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18 macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h22775 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_9_4_3_sh_mask.h26324 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_9_1_sh_mask.h24062 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_9_2_1_sh_mask.h24065 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_9_4_2_sh_mask.h21539 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_11_5_0_sh_mask.h31398 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_11_0_0_sh_mask.h35840 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_12_0_0_sh_mask.h21423 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_11_0_3_sh_mask.h39170 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_10_1_0_sh_mask.h33245 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro
Dgc_10_3_0_sh_mask.h32166 #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT … macro