Searched refs:RISCVRegisterInfo (Results 1 – 12 of 12) sorted by relevance
52 RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) in RISCVRegisterInfo() function in RISCVRegisterInfo57 RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { in getCalleeSavedRegs()84 BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { in getReservedRegs()121 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF, in isAsmClobberable()126 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const { in getNoPreservedMask()148 bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, in hasReservedSpillSlot()164 void RISCVRegisterInfo::adjustReg(MachineBasicBlock &MBB, in adjustReg()252 void RISCVRegisterInfo::lowerVSPILL(MachineBasicBlock::iterator II) const { in lowerVSPILL()321 void RISCVRegisterInfo::lowerVRELOAD(MachineBasicBlock::iterator II) const { in lowerVRELOAD()383 bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, in eliminateFrameIndex()[all …]
23 struct RISCVRegisterInfo : public RISCVGenRegisterInfo { struct25 RISCVRegisterInfo(unsigned HwMode);
61 RISCVRegisterInfo RegInfo;87 const RISCVRegisterInfo *getRegisterInfo() const override { in getRegisterInfo()
28 include "RISCVRegisterInfo.td"
340 const RISCVRegisterInfo &RI = *STI.getRegisterInfo(); in adjustStackForRVV()398 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); in emitPrologue()572 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); in emitPrologue()611 const RISCVRegisterInfo *RI = STI.getRegisterInfo(); in emitEpilogue()1076 const RISCVRegisterInfo *RegInfo = in processFunctionBeforeFrameFinalized()1171 const RISCVRegisterInfo &RI = *STI.getRegisterInfo(); in eliminateCallFramePseudoInstr()
38 RISCVRegisterInfo.cpp
27 // Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
26 struct RISCVRegisterInfo;597 const RISCVRegisterInfo *TRI);
1 //===-- RISCVRegisterInfo.td - RISC-V Register defs --------*- tablegen -*-===//
182 const RISCVRegisterInfo &TRI = *Subtarget.getRegisterInfo(); in RISCVTargetLowering()1672 const RISCVRegisterInfo *TRI) { in decomposeSubvectorInsertExtractToSubRegs()4725 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); in lowerFRAMEADDR()4748 const RISCVRegisterInfo &RI = *Subtarget.getRegisterInfo(); in lowerRETURNADDR()6170 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in lowerINSERT_SUBVECTOR()6328 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in lowerEXTRACT_SUBVECTOR()12804 const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo(); in isEligibleForTailCallOptimization()
31 RISCVRegisterInfo.cpp \
86 "RISCVRegisterInfo.cpp",