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Searched refs:REG_GET (Results 1 – 25 of 33) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/amd/display/dc/dce/
Ddce_panel_cntl.c58 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in dce_get_16_bit_backlight_from_pwm()
59 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in dce_get_16_bit_backlight_from_pwm()
62 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in dce_get_16_bit_backlight_from_pwm()
63 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in dce_get_16_bit_backlight_from_pwm()
99 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_panel_cntl_hw_init()
119 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_panel_cntl_hw_init()
153 REG_GET(PWRSEQ_CNTL, LVTMA_PWRSEQ_TARGET_STATE, &pwrseq_target_state); in dce_is_panel_backlight_on()
166 REG_GET(PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, &pwr_seq_state); in dce_is_panel_powered_on()
184 REG_GET(PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_store_backlight_level()
Ddce_i2c_hw.c74 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status()
121 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply()
133 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); in is_engine_available()
137 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); in is_engine_available()
148 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
364 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
Ddce_link_encoder.c241 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); in dce110_get_dig_frontend()
685 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dce110_is_dig_enabled()
1607 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1610 REG_GET(DP_MSE_SAT_UPDATE, in dce110_link_encoder_update_mst_stream_allocation_table()
1630 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dce110_link_encoder_connect_dig_be_to_fe()
Ddce_aux.c289 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, in read_channel_reply()
305 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); in read_channel_reply()
323 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); in read_channel_reply()
Ddce_mem_input.c734 dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, in dce_mi_allocate_dmif()
771 dmif_buffer_control = REG_GET(DMIF_BUFFER_CONTROL, in dce_mi_free_dmif()
828 REG_GET(GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, &update_pending); in dce_mi_is_flip_pending()
Ddce_clk_mgr.c157 REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); in dce_get_dp_ref_freq_khz()
162 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); in dce_get_dp_ref_freq_khz()
Ddce_opp.c586 REG_GET(CONTROL, in program_formatter_420_memory()
/openbsd/src/sys/dev/pci/drm/amd/display/dmub/src/
Ddmub_dcn31.c68 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn31_get_fb_base_offset()
71 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn31_get_fb_base_offset()
89 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn31_reset()
119 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); in dmub_dcn31_reset()
292 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); in dmub_dcn31_is_hw_init()
301 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn31_is_supported()
456 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn31_get_diagnostic_data()
459 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn31_get_diagnostic_data()
462 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn31_get_diagnostic_data()
465 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn31_get_diagnostic_data()
[all …]
Ddmub_dcn401.c48 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn401_get_fb_base_offset()
51 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn401_get_fb_base_offset()
69 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn401_reset()
304 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn401_is_hw_init()
313 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn401_is_supported()
451 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn401_get_diagnostic_data()
454 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn401_get_diagnostic_data()
457 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn401_get_diagnostic_data()
460 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn401_get_diagnostic_data()
463 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn401_get_diagnostic_data()
[all …]
Ddmub_dcn35.c73 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn35_get_fb_base_offset()
76 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn35_get_fb_base_offset()
94 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn35_reset()
124 REG_GET(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS, &pwait_mode); in dmub_dcn35_reset()
133 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enabled); in dmub_dcn35_reset()
343 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_enable); in dmub_dcn35_is_hw_init()
352 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn35_is_supported()
510 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn35_get_diagnostic_data()
513 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn35_get_diagnostic_data()
516 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn35_get_diagnostic_data()
[all …]
Ddmub_dcn20.c72 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn20_get_fb_base_offset()
75 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn20_get_fb_base_offset()
100 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn20_reset()
353 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn20_is_hw_init()
362 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn20_is_supported()
458 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn20_get_diagnostic_data()
461 REG_GET(DMCUB_CNTL, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn20_get_diagnostic_data()
464 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn20_get_diagnostic_data()
467 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn20_get_diagnostic_data()
470 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn20_get_diagnostic_data()
[all …]
Ddmub_dcn32.c74 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn32_get_fb_base_offset()
77 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn32_get_fb_base_offset()
95 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &in_reset); in dmub_dcn32_reset()
321 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_hw_init); in dmub_dcn32_is_hw_init()
330 REG_GET(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE, &supported); in dmub_dcn32_is_supported()
466 REG_GET(DMCUB_CNTL, DMCUB_ENABLE, &is_dmub_enabled); in dmub_dcn32_get_diagnostic_data()
469 REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); in dmub_dcn32_get_diagnostic_data()
472 REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); in dmub_dcn32_get_diagnostic_data()
475 REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); in dmub_dcn32_get_diagnostic_data()
478 REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled); in dmub_dcn32_get_diagnostic_data()
[all …]
Ddmub_dcn30.c72 REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp); in dmub_dcn30_get_fb_base_offset()
75 REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp); in dmub_dcn30_get_fb_base_offset()
Ddmub_reg.h111 #define REG_GET(reg_name, field, val) \ macro
/openbsd/src/sys/dev/pci/drm/amd/display/dc/gpio/
Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
Dhw_hpd.c76 REG_GET(int_status, in get_value()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dcn20/
Ddcn20_dwb.c177 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update()
204 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled()
205 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
Ddcn20_vmid.c61 REG_GET(PAGE_TABLE_BASE_ADDR_LO32, in dcn20_wait_for_vmid_ready()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/bios/
Dbios_parser_helper.c61 REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode); in bios_is_accelerated_mode()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/dcn21/
Ddcn21_link_encoder.c211 REG_GET(RDPCSTX_PHY_CNTL6, in dcn21_link_encoder_acquire_phy()
223 REG_GET(RDPCSTX_PHY_CNTL6, in dcn21_link_encoder_acquire_phy()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce100/
Ddce_clk_mgr.c138 REG_GET(DPREFCLK_CNTL, DPREFCLK_SRC_SEL, &dprefclk_src_sel); in dce_get_dp_ref_freq_khz()
143 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); in dce_get_dp_ref_freq_khz()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce60/
Ddce60_clk_mgr.c94 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider); in dce60_get_dp_ref_freq_khz()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/
Ddcn20_clk_mgr.c147 REG_GET(DENTIST_DISPCLK_CNTL, in dcn20_update_clocks_update_dentist()
433 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, &dispclk_wdivider); in dcn2_read_clocks_from_hw_dentist()
434 REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, &dppclk_wdivider); in dcn2_read_clocks_from_hw_dentist()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/inc/
Dreg_helper.h49 #ifdef REG_GET
50 #undef REG_GET
156 #define REG_GET(reg_name, field, val) \ macro
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c266 REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/ in get_vco_frequency_from_reg()
267 REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */ in get_vco_frequency_from_reg()

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