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Searched refs:R3 (Results 1 – 25 of 141) sorted by relevance

123456

/openbsd/src/gnu/usr.bin/binutils-2.17/opcodes/
Dia64-opc-a.c94 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
95 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY},
96 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
97 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY},
98 {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY},
99 {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY},
100 {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY},
101 {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
102 {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
103 {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY},
[all …]
Dia64-opc-i.c145 {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
146 {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
147 {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
148 {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
149 {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
150 {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
151 {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
152 {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
153 {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
154 {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
[all …]
Dv850-opc.c425 #define R3 (D16_16 + 1) macro
429 #define MOVCC (R3 + 1)
578 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
579 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
580 { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
589 { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 …
590 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 …
592 { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
593 { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 },
594 { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
[all …]
Dia64-opc-m.c119 {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY},
120 {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY},
121 {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}, EMPTY},
122 {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}, EMPTY},
123 {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY},
124 {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY},
125 {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY},
148 {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL},
149 {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL},
150 {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL},
[all …]
/openbsd/src/gnu/usr.bin/binutils/opcodes/
Dia64-opc-a.c93 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY},
94 {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY},
95 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY},
96 {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY},
97 {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY},
98 {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY},
99 {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY},
100 {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY},
101 {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
102 {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY},
[all …]
Dia64-opc-i.c135 {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
136 {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
137 {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
138 {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
139 {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
140 {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
141 {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
142 {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
143 {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
144 {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
[all …]
Dv850-opc.c500 #define R3 (D16_16 + 1) macro
504 #define MOVCC (R3 + 1)
653 { "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
654 { "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
655 { "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
664 { "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 …
665 { "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 …
667 { "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
668 { "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 },
669 { "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
[all …]
Dia64-opc-m.c118 {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY},
119 {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY},
120 {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}, EMPTY},
121 {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}, EMPTY},
122 {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY},
123 {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY},
124 {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY},
147 {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL},
148 {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL},
149 {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL},
[all …]
/openbsd/src/sys/lib/libsa/
Dsha1.c43 #define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30); macro
83 R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); in SHA1Transform()
84 R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); in SHA1Transform()
85 R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); in SHA1Transform()
86 R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); in SHA1Transform()
87 R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); in SHA1Transform()
/openbsd/src/sys/crypto/
Dsha1.c44 #define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30); macro
84 R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); in SHA1Transform()
85 R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); in SHA1Transform()
86 R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); in SHA1Transform()
87 R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); in SHA1Transform()
88 R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); in SHA1Transform()
/openbsd/src/lib/libc/hash/
Dsha1.c42 #define R3(v,w,x,y,z,i) z+=(((w|x)&y)|(w&x))+blk(i)+0x8F1BBCDC+rol(v,5);w=rol(w,30); macro
80 R3(a,b,c,d,e,40); R3(e,a,b,c,d,41); R3(d,e,a,b,c,42); R3(c,d,e,a,b,43); in SHA1Transform()
81 R3(b,c,d,e,a,44); R3(a,b,c,d,e,45); R3(e,a,b,c,d,46); R3(d,e,a,b,c,47); in SHA1Transform()
82 R3(c,d,e,a,b,48); R3(b,c,d,e,a,49); R3(a,b,c,d,e,50); R3(e,a,b,c,d,51); in SHA1Transform()
83 R3(d,e,a,b,c,52); R3(c,d,e,a,b,53); R3(b,c,d,e,a,54); R3(a,b,c,d,e,55); in SHA1Transform()
84 R3(e,a,b,c,d,56); R3(d,e,a,b,c,57); R3(c,d,e,a,b,58); R3(b,c,d,e,a,59); in SHA1Transform()
/openbsd/src/gnu/gcc/gcc/config/bfin/
Dlib1funcs.asm88 R3 = 0; define
93 R3 = ROT R3 BY 1; define
94 R2 = R3 - R1;
95 CC = R3 < R1 (IU);
98 IF ! CC R3 = R2;
115 R0 = R3;
/openbsd/src/lib/libcrypto/md5/asm/
Dmd5-586.pl141 sub R3 subroutine
258 &R3(-1,$A,$B,$C,$D,$X,48, 6,0xf4292244);
259 &R3( 0,$D,$A,$B,$C,$X,49,10,0x432aff97);
260 &R3( 0,$C,$D,$A,$B,$X,50,15,0xab9423a7);
261 &R3( 0,$B,$C,$D,$A,$X,51,21,0xfc93a039);
262 &R3( 0,$A,$B,$C,$D,$X,52, 6,0x655b59c3);
263 &R3( 0,$D,$A,$B,$C,$X,53,10,0x8f0ccc92);
264 &R3( 0,$C,$D,$A,$B,$X,54,15,0xffeff47d);
265 &R3( 0,$B,$C,$D,$A,$X,55,21,0x85845dd1);
266 &R3( 0,$A,$B,$C,$D,$X,56, 6,0x6fa87e4f);
[all …]
/openbsd/src/gnu/llvm/compiler-rt/lib/builtins/hexagon/
Dfastmath2_ldlib_asm.S54 #define mantb R3:2
55 #define lmantb R3:2
64 #define zero R3:2
153 #define mantb R3:2
154 #define lmantb R3:2
163 #define zero R3:2
258 #define mantbh R3
259 #define mantb R3:2
Dfastmath_dlib_asm.S61 #define mantexpb R3:2
62 #define lmantb R3:2
74 #define minus R3:2
196 #define mantexpb R3:2
197 #define lmantb R3:2
209 #define minus R3:2
325 #define mantbh R3
326 #define mantexpb R3:2
336 #define minus1 R3:2
Dfastmath2_dlib_asm.S59 #define mantexpb R3:2
60 #define lmantb R3:2
160 #define mantexpb R3:2
161 #define lmantb R3:2
261 #define mantbh R3
262 #define mantexpb R3:2
374 #define mant R3
456 #define mag R3
/openbsd/src/gnu/llvm/llvm/lib/Target/XCore/
DXCoreCallingConv.td15 // i32 are returned in registers R0, R1, R2, R3
16 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
34 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
DXCoreRegisterInfo.td28 def R3 : Ri< 3, "r3">, DwarfRegNum<[3]>;
46 (add R0, R1, R2, R3,
54 (add R0, R1, R2, R3,
/openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/
DPPCCallingConv.cpp37 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_AlignArgRegs()
62 PPC::R3, PPC::R4, PPC::R5, PPC::R6, in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
114 static const MCPhysReg HiRegList[] = { PPC::R3, PPC::R5, PPC::R7, PPC::R9 }; in CC_PPC32_SPE_CustomSplitFP64()
143 static const MCPhysReg HiRegList[] = { PPC::R3 }; in CC_PPC32_SPE_RetF64()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARC/
DARCCallingConv.td15 // i32 are returned in registers R0, R1, R2, R3
16 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3]>>,
32 CCIfType<[i32, i64], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7]>>,
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZInstrFormats.td184 // Assembly operands sometimes have a different order; in particular, R3 often
340 bits<4> R3;
345 let Inst{35-32} = R3;
357 bits<4> R3;
362 let Inst{35-32} = R3;
484 bits<4> R3;
490 let Inst{7-4} = R3;
515 bits<4> R3;
519 let Inst{15-12} = R3;
532 bits<4> R3;
[all …]
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DREADME.txt68 R3 = X + 15
75 load [i + R3]
77 Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
82 R3 = X + 15
91 R3 = X + 15 @ re-materialized
92 load [i + R3]
98 R3 = X + 15
/openbsd/src/gnu/llvm/llvm/lib/Target/BPF/
DBPFCallingConv.td22 CCIfType<[i64], CCAssignToReg<[ R1, R2, R3, R4, R5 ]>>,
38 [R1, R2, R3, R4, R5]>>,
41 CCIfType<[i64], CCAssignToRegWithShadow<[R1, R2, R3, R4, R5],
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMCallingConv.cpp24 static const MCPhysReg RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAPCS()
66 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64AssignAAPCS()
68 static const MCPhysReg GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; in f64AssignAAPCS()
75 assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64"); in f64AssignAAPCS()
117 static const MCPhysReg LoRegList[] = { ARM::R1, ARM::R3 }; in f64RetAssign()
153 static const MCPhysReg RRegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
DARMCallingConv.td40 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
64 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
65 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
121 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
138 CCAssignToReg<[R0, R1, R2, R3]>>>,
140 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>,
141 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>,
151 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
152 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>

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