Searched refs:PrevReg (Results 1 – 11 of 11) sorted by relevance
| /openbsd/src/gnu/llvm/clang/lib/StaticAnalyzer/Checkers/cert/ |
| D | InvalidPtrChecker.cpp | 125 const MemRegion *PrevReg = *Reg; in postPreviousReturnInvalidatingCall() local
126 State = State->add<InvalidMemoryRegions>(PrevReg); in postPreviousReturnInvalidatingCall()
127 Note = C.getNoteTag([PrevReg, FD](PathSensitiveBugReport &BR, in postPreviousReturnInvalidatingCall()
129 if (!BR.isInteresting(PrevReg)) in postPreviousReturnInvalidatingCall()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SILowerI1Copies.cpp | 88 unsigned DstReg, unsigned PrevReg, unsigned CurReg);
822 unsigned PrevReg, unsigned CurReg) { in buildMergeLaneMasks() argument
824 bool PrevConstant = isConstantLaneMask(PrevReg, PrevVal); in buildMergeLaneMasks()
845 PrevMaskedReg = PrevReg; in buildMergeLaneMasks()
849 .addReg(PrevReg) in buildMergeLaneMasks()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | RegAllocFast.cpp | 884 MCPhysReg PrevReg = LRI->PhysReg; in defineLiveThroughVirtReg() local
885 if (PrevReg != 0 && isRegUsedInInstr(PrevReg, true)) { in defineLiveThroughVirtReg()
886 LLVM_DEBUG(dbgs() << "Need new assignment for " << printReg(PrevReg, TRI) in defineLiveThroughVirtReg()
888 freePhysReg(PrevReg); in defineLiveThroughVirtReg()
894 << printReg(PrevReg, TRI) << '\n'); in defineLiveThroughVirtReg()
896 TII->get(TargetOpcode::COPY), PrevReg) in defineLiveThroughVirtReg()
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| D | RegAllocEvictionAdvisor.h | 124 Register canReassign(const LiveInterval &VirtReg, Register PrevReg) const;
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| D | ModuloSchedule.cpp | 562 unsigned PrevReg = 0; in generateExistingPhis() local
564 PrevReg = VRMap[PrevStage - np][LoopVal]; in generateExistingPhis()
566 NewReg, PrevReg); in generateExistingPhis()
1145 unsigned PrevReg) { in rewriteScheduledInstr() argument
1170 if (PrevReg && InProlog) in rewriteScheduledInstr()
1171 ReplaceReg = PrevReg; in rewriteScheduledInstr()
1172 else if (PrevReg && !isLoopCarried(*Phi) && in rewriteScheduledInstr()
1174 ReplaceReg = PrevReg; in rewriteScheduledInstr()
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| D | RegAllocGreedy.cpp | 448 Register PrevReg) const { in canReassign()
453 if ((*I).id() == PrevReg.id()) in canReassign()
469 << printReg(PrevReg, TRI) << " to " in canReassign()
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| D | MachinePipeliner.cpp | 2143 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
2144 if (!PrevReg) in canUseLastOffsetValue()
2148 MachineInstr *PrevDef = MRI.getVRegDef(PrevReg); in canUseLastOffsetValue()
2173 NewBase = PrevReg; in canUseLastOffsetValue()
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| /openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/ |
| D | ModuloSchedule.h | 232 unsigned NewReg, unsigned PrevReg = 0);
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 603 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
616 PrevReg = MCRegOp; in expandSET()
639 TmpInst.addOperand(PrevReg); in expandSET()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4394 unsigned PrevReg = FirstReg; in tryParseMatrixTileList() local
4415 if (RI->getEncodingValue(Reg) <= (RI->getEncodingValue(PrevReg))) in tryParseMatrixTileList()
4425 PrevReg = Reg; in tryParseMatrixTileList()
4492 int64_t PrevReg = FirstReg; in tryParseVectorList() local
4512 (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + NumRegs - PrevReg); in tryParseVectorList()
4539 getContext().getRegisterInfo()->getEncodingValue(PrevReg); in tryParseVectorList()
4552 PrevReg = Reg; in tryParseVectorList()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1430 int PrevReg = *RegList.List->begin(); in isRegList16() local
1433 if ( Reg != PrevReg + 1) in isRegList16()
1435 PrevReg = Reg; in isRegList16()
6838 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
6857 unsigned TmpReg = PrevReg + 1; in parseRegisterList()
6866 PrevReg = TmpReg; in parseRegisterList()
6873 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6886 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6910 PrevReg = RegNo; in parseRegisterList()
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