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Searched refs:PostRAScheduler (Results 1 – 25 of 31) sorted by relevance

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/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DPostRASchedulerList.cpp76 class PostRAScheduler : public MachineFunctionPass { class
82 PostRAScheduler() : MachineFunctionPass(ID) {} in PostRAScheduler() function in __anon1992e0240111::PostRAScheduler
108 char PostRAScheduler::ID = 0;
197 char &llvm::PostRASchedulerID = PostRAScheduler::ID;
199 INITIALIZE_PASS(PostRAScheduler, DEBUG_TYPE,
262 bool PostRAScheduler::enablePostRAScheduler( in enablePostRAScheduler()
278 bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { in runOnMachineFunction()
DTargetSubtargetInfo.cpp49 return getSchedModel().PostRAScheduler; in enablePostRAScheduler()
/openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/
DLanaiSchedule.td45 let PostRAScheduler = 0;
/openbsd/src/gnu/llvm/llvm/include/llvm/MC/
DMCSchedule.h300 bool PostRAScheduler; // default value is false member
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMScheduleM4.td18 let PostRAScheduler = 1;
DARMScheduleM55.td89 let PostRAScheduler = 1;
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86Schedule.td736 // and disables PostRAScheduler.
742 let PostRAScheduler = 0;
748 // Define a model with the PostRAScheduler enabled.
750 let PostRAScheduler = 1;
DX86ScheduleSLM.td21 let PostRAScheduler = 1;
DX86ScheduleAtom.td28 let PostRAScheduler = 1;
DX86ScheduleZnver3.td38 // FIXME: PR50584: MachineScheduler/PostRAScheduler have quadradic complexity,
62 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
DX86ScheduleBtVer2.td23 let PostRAScheduler = 1;
DX86ScheduleZnver4.td34 // FIXME: PR50584: MachineScheduler/PostRAScheduler have quadradic complexity,
60 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
DX86ScheduleZnver2.td22 let PostRAScheduler = 1;
DX86ScheduleZnver1.td22 let PostRAScheduler = 1;
DX86ScheduleBdVer2.td29 let PostRAScheduler = 1; // Enable Post RegAlloc Scheduler pass.
DX86.td1388 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DSISchedule.td79 let PostRAScheduler = 1;
/openbsd/src/gnu/llvm/llvm/utils/TableGen/
DSubtargetEmitter.cpp1392 bool PostRAScheduler = in EmitProcessorModels() local
1395 OS << " " << (PostRAScheduler ? "true" : "false") << ", // " in EmitProcessorModels()
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64SchedThunderX.td25 let PostRAScheduler = 1; // Use PostRA scheduler.
DAArch64SchedA55.td29 let PostRAScheduler = 1; // Enable PostRA scheduler pass.
DAArch64SchedThunderX3T110.td24 let PostRAScheduler = 1; // Using PostRA sched.
/openbsd/src/gnu/llvm/llvm/include/llvm/Target/
DTargetSchedule.td88 bit PostRAScheduler = false; // Enable Post RegAlloc Scheduler pass.
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZScheduleZ196.td24 let PostRAScheduler = 1;
DSystemZScheduleZEC12.td24 let PostRAScheduler = 1;
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsScheduleGeneric.td28 let PostRAScheduler = 1;

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