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Searched refs:PPCLK_DISPCLK (Results 1 – 7 of 7) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
Dvega20_processpptables.c249 pptable->DpmDescriptor[PPCLK_DISPCLK].VoltageMode,
250 pptable->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete,
251 pptable->DpmDescriptor[PPCLK_DISPCLK].NumDiscreteLevels,
252 pptable->DpmDescriptor[PPCLK_DISPCLK].padding,
253 pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.m,
254 pptable->DpmDescriptor[PPCLK_DISPCLK].ConversionToAvfsClk.b,
255 pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.a,
256 pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.b,
257 pptable->DpmDescriptor[PPCLK_DISPCLK].SsCurve.c);
362 pr_info("DcModeMaxFreq[PPCLK_DISPCLK] = %d\n", pptable->DcModeMaxFreq[PPCLK_DISPCLK]);
Dvega20_hwmgr.c745 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); in vega20_setup_default_dpm_tables()
1649 PPCLK_DISPCLK)) == 0, in vega20_init_max_sustainable_clocks()
2314 clk_select = PPCLK_DISPCLK; in vega20_display_clock_voltage_request()
Dvega12_hwmgr.c758 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK); in vega12_setup_default_dpm_tables()
1589 clk_select = PPCLK_DISPCLK; in vega12_display_clock_voltage_request()
/openbsd/src/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
Ddcn30_smu11_driver_if.h17 PPCLK_DISPCLK, enumerator
Ddcn30_clk_mgr.c149 dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK, in dcn3_init_clocks()
296 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_… in dcn3_update_clocks()
/openbsd/src/sys/dev/pci/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c159 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
1108 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete; in navi10_set_default_dpm_table()
Dsienna_cichlid_ppt.c176 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
1125 !table_member[PPCLK_DISPCLK].SnapToDiscrete; in sienna_cichlid_set_default_dpm_table()