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Searched refs:PIPE_A (Results 1 – 25 of 44) sorted by relevance

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/openbsd/src/sys/dev/pci/drm/i915/
Dintel_gvt_mmio_table.c129 MMIO_D(PIPEDSL(dev_priv, PIPE_A)); in iterate_generic_mmio()
137 MMIO_D(PIPESTAT(dev_priv, PIPE_A)); in iterate_generic_mmio()
141 MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_A)); in iterate_generic_mmio()
145 MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A)); in iterate_generic_mmio()
149 MMIO_D(CURCNTR(dev_priv, PIPE_A)); in iterate_generic_mmio()
152 MMIO_D(CURPOS(dev_priv, PIPE_A)); in iterate_generic_mmio()
155 MMIO_D(CURBASE(dev_priv, PIPE_A)); in iterate_generic_mmio()
158 MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_A)); in iterate_generic_mmio()
168 MMIO_D(DSPCNTR(dev_priv, PIPE_A)); in iterate_generic_mmio()
169 MMIO_D(DSPADDR(dev_priv, PIPE_A)); in iterate_generic_mmio()
[all …]
Dintel_clock_gating.c317 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
425 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in bdw_init_clock_gating()
472 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in hsw_init_clock_gating()
Di915_irq.c903 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
1085 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
1210 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in i965_irq_postinstall()
1211 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/openbsd/src/sys/dev/pci/drm/i915/display/
Dintel_pch_display.c25 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
33 return PIPE_A; in intel_crtc_pch_transcoder()
120 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
128 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
139 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
147 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()
550 assert_fdi_rx_enabled(dev_priv, PIPE_A); in lpt_enable_pch_transcoder()
552 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
558 intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
584 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
[all …]
Dintel_fdi.c220 case PIPE_A: in ilk_check_fdi_lanes()
447 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
899 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
909 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
910 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
915 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
944 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
948 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
949 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
955 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
[all …]
Dskl_watermark.c861 .active_pipes = BIT(PIPE_A),
863 [PIPE_A] = BIT(DBUF_S1),
873 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
875 [PIPE_A] = BIT(DBUF_S1),
886 .active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
888 [PIPE_A] = BIT(DBUF_S1),
900 .active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
902 [PIPE_A] = BIT(DBUF_S1),
924 .active_pipes = BIT(PIPE_A),
926 [PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
[all …]
Dintel_display_device.c147 [PIPE_A] = CURSOR_A_OFFSET, \
152 [PIPE_A] = CURSOR_A_OFFSET, \
158 [PIPE_A] = CURSOR_A_OFFSET, \
165 [PIPE_A] = CURSOR_A_OFFSET, \
172 [PIPE_A] = CURSOR_A_OFFSET, \
218 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
231 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
279 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
358 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
411 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
[all …]
Dintel_display_limits.h17 PIPE_A = 0, enumerator
34 TRANSCODER_A = PIPE_A,
Dg4x_hdmi.c410 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
411 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_disable_hdmi()
414 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
428 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_disable_hdmi()
429 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
430 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_disable_hdmi()
771 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
Dintel_cursor.c304 intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); in i845_cursor_update_arm()
305 intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base); in i845_cursor_update_arm()
306 intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size); in i845_cursor_update_arm()
307 intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); in i845_cursor_update_arm()
308 intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); in i845_cursor_update_arm()
314 intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); in i845_cursor_update_arm()
332 power_domain = POWER_DOMAIN_PIPE(PIPE_A); in i845_cursor_get_hw_state()
337 ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
339 *pipe = PIPE_A; in i845_cursor_get_hw_state()
Dintel_display_reg_defs.h40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
46 DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
Di9xx_wm.c270 case PIPE_A: in vlv_get_fifo_size()
727 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
733 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
734 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
777 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
779 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
780 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
781 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
803 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
804 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Dg4x_dp.c274 *pipe = PIPE_A; in cpt_dp_port_selected()
459 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
460 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in intel_dp_link_down()
464 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
473 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); in intel_dp_link_down()
474 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
475 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in intel_dp_link_down()
1402 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
Dintel_crt.c248 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_disable_crt()
277 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_post_disable_crt()
289 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); in hsw_pre_pll_enable_crt()
334 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); in hsw_enable_crt()
1069 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1135 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Dintel_pipe_crc.c175 case PIPE_A: in vlv_pipe_crc_ctl_reg()
236 case PIPE_A: in vlv_undo_pipe_scramble_reset()
310 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
Dintel_display_power_well.c1051 if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1052 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
1061 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
1067 return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1207 if (pipe != PIPE_A) in vlv_display_power_well_init()
1496 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1651 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1682 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
Dintel_dmc_regs.h22 #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
Dintel_fifo_underrun.c139 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
227 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
Dintel_dpll.c398 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
1431 if (crtc->pipe != PIPE_A) in vlv_dpll()
1457 if (crtc->pipe != PIPE_A) in chv_dpll()
1964 if (pipe == PIPE_A) in vlv_prepare_pll()
1972 if (pipe == PIPE_A) in vlv_prepare_pll()
2175 if (pipe != PIPE_A) { in chv_enable_pll()
2249 if (pipe != PIPE_A) in vlv_disable_pll()
2267 if (pipe != PIPE_A) in chv_disable_pll()
Dintel_display_irq.c295 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
446 case PIPE_A: in i9xx_pipestat_irq_ack()
622 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A); in ibx_irq_handler()
1001 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1474 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
Dintel_pps.c41 case PIPE_A: in pps_name()
172 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
229 pipe = PIPE_A; in vlv_power_sequencer_pipe()
300 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1159 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
Dhsw_ips.c184 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
/openbsd/src/sys/dev/pci/drm/i915/gvt/
Dhandlers.c699 vgpu->id, pipe_name(PIPE_A), new_rate); in vgpu_update_refresh_rate()
899 calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C))
902 calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C))
905 calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C))
1013 calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C))
1036 calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C))
2282 MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); in init_generic_mmio_info()
2283 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2291 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); in init_generic_mmio_info()
2292 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
[all …]
Dreg.h68 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
78 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
Ddisplay.c54 pipe = PIPE_A; in get_edp_pipe()
83 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
634 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
640 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()

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