1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #include <asm/byteorder.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33
34 #include "atomfirmware.h"
35
36 //<DMUB_TYPES>==================================================================
37 /* Basic type definitions. */
38
39 #define __forceinline inline
40
41 /**
42 * Flag from driver to indicate that ABM should be disabled gradually
43 * by slowly reversing all backlight programming and pixel compensation.
44 */
45 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
46
47 /**
48 * Flag from driver to indicate that ABM should be disabled immediately
49 * and undo all backlight programming and pixel compensation.
50 */
51 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
52
53 /**
54 * Flag from driver to indicate that ABM should be disabled immediately
55 * and keep the current backlight programming and pixel compensation.
56 */
57 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
58
59 /**
60 * Flag from driver to set the current ABM pipe index or ABM operating level.
61 */
62 #define SET_ABM_PIPE_NORMAL 1
63
64 /**
65 * Number of ambient light levels in ABM algorithm.
66 */
67 #define NUM_AMBI_LEVEL 5
68
69 /**
70 * Number of operating/aggression levels in ABM algorithm.
71 */
72 #define NUM_AGGR_LEVEL 4
73
74 /**
75 * Number of segments in the gamma curve.
76 */
77 #define NUM_POWER_FN_SEGS 8
78
79 /**
80 * Number of segments in the backlight curve.
81 */
82 #define NUM_BL_CURVE_SEGS 16
83
84 /**
85 * Maximum number of segments in ABM ACE curve.
86 */
87 #define ABM_MAX_NUM_OF_ACE_SEGMENTS 64
88
89 /**
90 * Maximum number of bins in ABM histogram.
91 */
92 #define ABM_MAX_NUM_OF_HG_BINS 64
93
94 /* Maximum number of SubVP streams */
95 #define DMUB_MAX_SUBVP_STREAMS 2
96
97 /* Define max FPO streams as 4 for now. Current implementation today
98 * only supports 1, but could be more in the future. Reduce array
99 * size to ensure the command size remains less than 64 bytes if
100 * adding new fields.
101 */
102 #define DMUB_MAX_FPO_STREAMS 4
103
104 /* Maximum number of streams on any ASIC. */
105 #define DMUB_MAX_STREAMS 6
106
107 /* Maximum number of planes on any ASIC. */
108 #define DMUB_MAX_PLANES 6
109
110 /* Maximum number of phantom planes on any ASIC */
111 #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2)
112
113 /* Trace buffer offset for entry */
114 #define TRACE_BUFFER_ENTRY_OFFSET 16
115
116 /**
117 * Maximum number of dirty rects supported by FW.
118 */
119 #define DMUB_MAX_DIRTY_RECTS 3
120
121 /**
122 *
123 * PSR control version legacy
124 */
125 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
126 /**
127 * PSR control version with multi edp support
128 */
129 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
130
131
132 /**
133 * ABM control version legacy
134 */
135 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
136
137 /**
138 * ABM control version with multi edp support
139 */
140 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
141
142 /**
143 * Physical framebuffer address location, 64-bit.
144 */
145 #ifndef PHYSICAL_ADDRESS_LOC
146 #define PHYSICAL_ADDRESS_LOC union large_integer
147 #endif
148
149 /**
150 * OS/FW agnostic memcpy
151 */
152 #ifndef dmub_memcpy
153 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
154 #endif
155
156 /**
157 * OS/FW agnostic memset
158 */
159 #ifndef dmub_memset
160 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
161 #endif
162
163 #pragma pack(push, 1)
164 /**
165 * OS/FW agnostic udelay
166 */
167 #ifndef dmub_udelay
168 #define dmub_udelay(microseconds) udelay(microseconds)
169 #endif
170
171 #pragma pack(push, 1)
172 #define ABM_NUM_OF_ACE_SEGMENTS 5
173
174 union abm_flags {
175 struct {
176 /**
177 * @abm_enabled: Indicates if ABM is enabled.
178 */
179 unsigned int abm_enabled : 1;
180
181 /**
182 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
183 */
184 unsigned int disable_abm_requested : 1;
185
186 /**
187 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled immediately.
188 */
189 unsigned int disable_abm_immediately : 1;
190
191 /**
192 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
193 * to be disabled immediately and keep gain.
194 */
195 unsigned int disable_abm_immediate_keep_gain : 1;
196
197 /**
198 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
199 */
200 unsigned int fractional_pwm : 1;
201
202 /**
203 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
204 * of user backlight level.
205 */
206 unsigned int abm_gradual_bl_change : 1;
207
208 /**
209 * @abm_new_frame: Indicates if a new frame update needed for ABM to ramp up into steady
210 */
211 unsigned int abm_new_frame : 1;
212
213 /**
214 * @vb_scaling_enabled: Indicates variBright Scaling Enable
215 */
216 unsigned int vb_scaling_enabled : 1;
217 } bitfields;
218
219 unsigned int u32All;
220 };
221 #pragma pack(pop)
222
223 struct abm_save_restore {
224 /**
225 * @flags: Misc. ABM flags.
226 */
227 union abm_flags flags;
228
229 /**
230 * @pause: true: pause ABM and get state
231 * false: unpause ABM after setting state
232 */
233 uint32_t pause;
234
235 /**
236 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
237 */
238 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
239
240 /**
241 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
242 */
243 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
244
245 /**
246 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
247 */
248 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
249
250
251 /**
252 * @knee_threshold: Current x-position of ACE knee (u0.16).
253 */
254 uint32_t knee_threshold;
255 /**
256 * @current_gain: Current backlight reduction (u16.16).
257 */
258 uint32_t current_gain;
259 /**
260 * @curr_bl_level: Current actual backlight level converging to target backlight level.
261 */
262 uint16_t curr_bl_level;
263
264 /**
265 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
266 */
267 uint16_t curr_user_bl_level;
268
269 };
270
271 /**
272 * union dmub_addr - DMUB physical/virtual 64-bit address.
273 */
274 union dmub_addr {
275 struct {
276 uint32_t low_part; /**< Lower 32 bits */
277 uint32_t high_part; /**< Upper 32 bits */
278 } u; /*<< Low/high bit access */
279 uint64_t quad_part; /*<< 64 bit address */
280 };
281 #pragma pack(pop)
282
283 /**
284 * Dirty rect definition.
285 */
286 struct dmub_rect {
287 /**
288 * Dirty rect x offset.
289 */
290 uint32_t x;
291
292 /**
293 * Dirty rect y offset.
294 */
295 uint32_t y;
296
297 /**
298 * Dirty rect width.
299 */
300 uint32_t width;
301
302 /**
303 * Dirty rect height.
304 */
305 uint32_t height;
306 };
307
308 /**
309 * Flags that can be set by driver to change some PSR behaviour.
310 */
311 union dmub_psr_debug_flags {
312 /**
313 * Debug flags.
314 */
315 struct {
316 /**
317 * Enable visual confirm in FW.
318 */
319 uint32_t visual_confirm : 1;
320
321 /**
322 * Force all selective updates to bw full frame updates.
323 */
324 uint32_t force_full_frame_update : 1;
325
326 /**
327 * Use HW Lock Mgr object to do HW locking in FW.
328 */
329 uint32_t use_hw_lock_mgr : 1;
330
331 /**
332 * Use TPS3 signal when restore main link.
333 */
334 uint32_t force_wakeup_by_tps3 : 1;
335
336 /**
337 * Back to back flip, therefore cannot power down PHY
338 */
339 uint32_t back_to_back_flip : 1;
340
341 /**
342 * Enable visual confirm for IPS
343 */
344 uint32_t enable_ips_visual_confirm : 1;
345 } bitfields;
346
347 /**
348 * Union for debug flags.
349 */
350 uint32_t u32All;
351 };
352
353 /**
354 * Flags that can be set by driver to change some Replay behaviour.
355 */
356 union replay_debug_flags {
357 struct {
358 /**
359 * 0x1 (bit 0)
360 * Enable visual confirm in FW.
361 */
362 uint32_t visual_confirm : 1;
363
364 /**
365 * 0x2 (bit 1)
366 * @skip_crc: Set if need to skip CRC.
367 */
368 uint32_t skip_crc : 1;
369
370 /**
371 * 0x4 (bit 2)
372 * @force_link_power_on: Force disable ALPM control
373 */
374 uint32_t force_link_power_on : 1;
375
376 /**
377 * 0x8 (bit 3)
378 * @force_phy_power_on: Force phy power on
379 */
380 uint32_t force_phy_power_on : 1;
381
382 /**
383 * 0x10 (bit 4)
384 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
385 */
386 uint32_t timing_resync_disabled : 1;
387
388 /**
389 * 0x20 (bit 5)
390 * @skip_crtc_disabled: CRTC disable skipped
391 */
392 uint32_t skip_crtc_disabled : 1;
393
394 /**
395 * 0x40 (bit 6)
396 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
397 */
398 uint32_t force_defer_one_frame_update : 1;
399
400 /**
401 * 0x80 (bit 7)
402 * @disable_delay_alpm_on: Force disable delay alpm on
403 */
404 uint32_t disable_delay_alpm_on : 1;
405
406 /**
407 * 0x100 (bit 8)
408 * @disable_desync_error_check: Force disable desync error check
409 */
410 uint32_t disable_desync_error_check : 1;
411
412 /**
413 * 0x200 (bit 9)
414 * @force_self_update_when_abm_non_steady: Force self update if abm is not steady
415 */
416 uint32_t force_self_update_when_abm_non_steady : 1;
417
418 /**
419 * 0x400 (bit 10)
420 * @enable_ips_visual_confirm: Enable IPS visual confirm when entering IPS
421 * If we enter IPS2, the Visual confirm bar will change to yellow
422 */
423 uint32_t enable_ips_visual_confirm : 1;
424
425 /**
426 * 0x800 (bit 11)
427 * @enable_ips_residency_profiling: Enable IPS residency profiling
428 */
429 uint32_t enable_ips_residency_profiling : 1;
430
431 uint32_t reserved : 20;
432 } bitfields;
433
434 uint32_t u32All;
435 };
436
437 union replay_hw_flags {
438 struct {
439 /**
440 * @allow_alpm_fw_standby_mode: To indicate whether the
441 * ALPM FW standby mode is allowed
442 */
443 uint32_t allow_alpm_fw_standby_mode : 1;
444
445 /*
446 * @dsc_enable_status: DSC enable status in driver
447 */
448 uint32_t dsc_enable_status : 1;
449
450 /**
451 * @fec_enable_status: receive fec enable/disable status from driver
452 */
453 uint32_t fec_enable_status : 1;
454
455 /*
456 * @smu_optimizations_en: SMU power optimization.
457 * Only when active display is Replay capable and display enters Replay.
458 * Trigger interrupt to SMU to powerup/down.
459 */
460 uint32_t smu_optimizations_en : 1;
461
462 /**
463 * @phy_power_state: Indicates current phy power state
464 */
465 uint32_t phy_power_state : 1;
466
467 /**
468 * @link_power_state: Indicates current link power state
469 */
470 uint32_t link_power_state : 1;
471 /**
472 * Use TPS3 signal when restore main link.
473 */
474 uint32_t force_wakeup_by_tps3 : 1;
475 } bitfields;
476
477 uint32_t u32All;
478 };
479
480 /**
481 * DMUB feature capabilities.
482 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
483 */
484 struct dmub_feature_caps {
485 /**
486 * Max PSR version supported by FW.
487 */
488 uint8_t psr;
489 uint8_t fw_assisted_mclk_switch_ver;
490 uint8_t reserved[4];
491 uint8_t subvp_psr_support;
492 uint8_t gecc_enable;
493 uint8_t replay_supported;
494 uint8_t replay_reserved[3];
495 };
496
497 struct dmub_visual_confirm_color {
498 /**
499 * Maximum 10 bits color value
500 */
501 uint16_t color_r_cr;
502 uint16_t color_g_y;
503 uint16_t color_b_cb;
504 uint16_t panel_inst;
505 };
506
507 //==============================================================================
508 //</DMUB_TYPES>=================================================================
509 //==============================================================================
510 //< DMUB_META>==================================================================
511 //==============================================================================
512 #pragma pack(push, 1)
513
514 /* Magic value for identifying dmub_fw_meta_info */
515 #define DMUB_FW_META_MAGIC 0x444D5542
516
517 /* Offset from the end of the file to the dmub_fw_meta_info */
518 #define DMUB_FW_META_OFFSET 0x24
519
520 /**
521 * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization
522 */
523 union dmub_fw_meta_feature_bits {
524 struct {
525 uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */
526 uint32_t reserved : 31;
527 } bits; /**< status bits */
528 uint32_t all; /**< 32-bit access to status bits */
529 };
530
531 /**
532 * struct dmub_fw_meta_info - metadata associated with fw binary
533 *
534 * NOTE: This should be considered a stable API. Fields should
535 * not be repurposed or reordered. New fields should be
536 * added instead to extend the structure.
537 *
538 * @magic_value: magic value identifying DMUB firmware meta info
539 * @fw_region_size: size of the firmware state region
540 * @trace_buffer_size: size of the tracebuffer region
541 * @fw_version: the firmware version information
542 * @dal_fw: 1 if the firmware is DAL
543 * @shared_state_size: size of the shared state region in bytes
544 * @shared_state_features: number of shared state features
545 */
546 struct dmub_fw_meta_info {
547 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
548 uint32_t fw_region_size; /**< size of the firmware state region */
549 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
550 uint32_t fw_version; /**< the firmware version information */
551 uint8_t dal_fw; /**< 1 if the firmware is DAL */
552 uint8_t reserved[3]; /**< padding bits */
553 uint32_t shared_state_size; /**< size of the shared state region in bytes */
554 uint16_t shared_state_features; /**< number of shared state features */
555 uint16_t reserved2; /**< padding bytes */
556 union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */
557 };
558
559 /**
560 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
561 */
562 union dmub_fw_meta {
563 struct dmub_fw_meta_info info; /**< metadata info */
564 uint8_t reserved[64]; /**< padding bits */
565 };
566
567 #pragma pack(pop)
568
569 //==============================================================================
570 //< DMUB Trace Buffer>================================================================
571 //==============================================================================
572 #if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)
573 /**
574 * dmub_trace_code_t - firmware trace code, 32-bits
575 */
576 typedef uint32_t dmub_trace_code_t;
577
578 /**
579 * struct dmcub_trace_buf_entry - Firmware trace entry
580 */
581 struct dmcub_trace_buf_entry {
582 dmub_trace_code_t trace_code; /**< trace code for the event */
583 uint32_t tick_count; /**< the tick count at time of trace */
584 uint32_t param0; /**< trace defined parameter 0 */
585 uint32_t param1; /**< trace defined parameter 1 */
586 };
587 #endif
588
589 //==============================================================================
590 //< DMUB_STATUS>================================================================
591 //==============================================================================
592
593 /**
594 * DMCUB scratch registers can be used to determine firmware status.
595 * Current scratch register usage is as follows:
596 *
597 * SCRATCH0: FW Boot Status register
598 * SCRATCH5: LVTMA Status Register
599 * SCRATCH15: FW Boot Options register
600 */
601
602 /**
603 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
604 */
605 union dmub_fw_boot_status {
606 struct {
607 uint32_t dal_fw : 1; /**< 1 if DAL FW */
608 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
609 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
610 uint32_t restore_required : 1; /**< 1 if driver should call restore */
611 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
612 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
613 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
614 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
615 uint32_t ono_regions_enabled: 1; /**< 1 if ONO regions are enabled */
616 } bits; /**< status bits */
617 uint32_t all; /**< 32-bit access to status bits */
618 };
619
620 /**
621 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
622 */
623 enum dmub_fw_boot_status_bit {
624 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
625 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
626 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
627 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
628 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
629 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
630 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
631 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
632 DMUB_FW_BOOT_STATUS_BIT_ONO_REGIONS_ENABLED = (1 << 8), /**< 1 if ONO regions are enabled */
633 };
634
635 /* Register bit definition for SCRATCH5 */
636 union dmub_lvtma_status {
637 struct {
638 uint32_t psp_ok : 1;
639 uint32_t edp_on : 1;
640 uint32_t reserved : 30;
641 } bits;
642 uint32_t all;
643 };
644
645 enum dmub_lvtma_status_bit {
646 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
647 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
648 };
649
650 enum dmub_ips_disable_type {
651 DMUB_IPS_ENABLE = 0,
652 DMUB_IPS_DISABLE_ALL = 1,
653 DMUB_IPS_DISABLE_IPS1 = 2,
654 DMUB_IPS_DISABLE_IPS2 = 3,
655 DMUB_IPS_DISABLE_IPS2_Z10 = 4,
656 DMUB_IPS_DISABLE_DYNAMIC = 5,
657 DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF = 6,
658 };
659
660 #define DMUB_IPS1_ALLOW_MASK 0x00000001
661 #define DMUB_IPS2_ALLOW_MASK 0x00000002
662 #define DMUB_IPS1_COMMIT_MASK 0x00000004
663 #define DMUB_IPS2_COMMIT_MASK 0x00000008
664
665 /**
666 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
667 */
668 union dmub_fw_boot_options {
669 struct {
670 uint32_t pemu_env : 1; /**< 1 if PEMU */
671 uint32_t fpga_env : 1; /**< 1 if FPGA */
672 uint32_t optimized_init : 1; /**< 1 if optimized init */
673 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
674 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
675 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
676 uint32_t z10_disable: 1; /**< 1 to disable z10 */
677 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
678 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
679 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
680 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled on DCN31 */
681 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
682 uint32_t power_optimization: 1;
683 uint32_t diag_env: 1; /* 1 if diagnostic environment */
684 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
685 uint32_t usb4_cm_version: 1; /**< 1 CM support */
686 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
687 uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/
688 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
689 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
690 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
691 uint32_t ips_disable: 3; /* options to disable ips support*/
692 uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
693 uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
694 uint32_t reserved : 7; /**< reserved */
695 } bits; /**< boot bits */
696 uint32_t all; /**< 32-bit access to bits */
697 };
698
699 enum dmub_fw_boot_options_bit {
700 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
701 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
702 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
703 };
704
705 //==============================================================================
706 //< DMUB_SHARED_STATE>==========================================================
707 //==============================================================================
708
709 /**
710 * Shared firmware state between driver and firmware for lockless communication
711 * in situations where the inbox/outbox may be unavailable.
712 *
713 * Each structure *must* be at most 256-bytes in size. The layout allocation is
714 * described below:
715 *
716 * [Header (256 Bytes)][Feature 1 (256 Bytes)][Feature 2 (256 Bytes)]...
717 */
718
719 /**
720 * enum dmub_shared_state_feature_id - List of shared state features.
721 */
722 enum dmub_shared_state_feature_id {
723 DMUB_SHARED_SHARE_FEATURE__INVALID = 0,
724 DMUB_SHARED_SHARE_FEATURE__IPS_FW = 1,
725 DMUB_SHARED_SHARE_FEATURE__IPS_DRIVER = 2,
726 DMUB_SHARED_STATE_FEATURE__LAST, /* Total number of features. */
727 };
728
729 /**
730 * struct dmub_shared_state_ips_fw - Firmware signals for IPS.
731 */
732 union dmub_shared_state_ips_fw_signals {
733 struct {
734 uint32_t ips1_commit : 1; /**< 1 if in IPS1 */
735 uint32_t ips2_commit : 1; /**< 1 if in IPS2 */
736 uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */
737 uint32_t detection_required : 1; /**< 1 if detection is required */
738 uint32_t reserved_bits : 28; /**< Reversed */
739 } bits;
740 uint32_t all;
741 };
742
743 /**
744 * struct dmub_shared_state_ips_signals - Firmware signals for IPS.
745 */
746 union dmub_shared_state_ips_driver_signals {
747 struct {
748 uint32_t allow_pg : 1; /**< 1 if PG is allowed */
749 uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */
750 uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */
751 uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */
752 uint32_t allow_idle : 1; /**< 1 if driver is allowing idle */
753 uint32_t reserved_bits : 27; /**< Reversed bits */
754 } bits;
755 uint32_t all;
756 };
757
758 /**
759 * IPS FW Version
760 */
761 #define DMUB_SHARED_STATE__IPS_FW_VERSION 1
762
763 /**
764 * struct dmub_shared_state_ips_fw - Firmware state for IPS.
765 */
766 struct dmub_shared_state_ips_fw {
767 union dmub_shared_state_ips_fw_signals signals; /**< 4 bytes, IPS signal bits */
768 uint32_t rcg_entry_count; /**< Entry counter for RCG */
769 uint32_t rcg_exit_count; /**< Exit counter for RCG */
770 uint32_t ips1_entry_count; /**< Entry counter for IPS1 */
771 uint32_t ips1_exit_count; /**< Exit counter for IPS1 */
772 uint32_t ips2_entry_count; /**< Entry counter for IPS2 */
773 uint32_t ips2_exit_count; /**< Exit counter for IPS2 */
774 uint32_t reserved[55]; /**< Reversed, to be updated when adding new fields. */
775 }; /* 248-bytes, fixed */
776
777 /**
778 * IPS Driver Version
779 */
780 #define DMUB_SHARED_STATE__IPS_DRIVER_VERSION 1
781
782 /**
783 * struct dmub_shared_state_ips_driver - Driver state for IPS.
784 */
785 struct dmub_shared_state_ips_driver {
786 union dmub_shared_state_ips_driver_signals signals; /**< 4 bytes, IPS signal bits */
787 uint32_t reserved[61]; /**< Reversed, to be updated when adding new fields. */
788 }; /* 248-bytes, fixed */
789
790 /**
791 * enum dmub_shared_state_feature_common - Generic payload.
792 */
793 struct dmub_shared_state_feature_common {
794 uint32_t padding[62];
795 }; /* 248-bytes, fixed */
796
797 /**
798 * enum dmub_shared_state_feature_header - Feature description.
799 */
800 struct dmub_shared_state_feature_header {
801 uint16_t id; /**< Feature ID */
802 uint16_t version; /**< Feature version */
803 uint32_t reserved; /**< Reserved bytes. */
804 }; /* 8 bytes, fixed */
805
806 /**
807 * struct dmub_shared_state_feature_block - Feature block.
808 */
809 struct dmub_shared_state_feature_block {
810 struct dmub_shared_state_feature_header header; /**< Shared state header. */
811 union dmub_shared_feature_state_union {
812 struct dmub_shared_state_feature_common common; /**< Generic data */
813 struct dmub_shared_state_ips_fw ips_fw; /**< IPS firmware state */
814 struct dmub_shared_state_ips_driver ips_driver; /**< IPS driver state */
815 } data; /**< Shared state data. */
816 }; /* 256-bytes, fixed */
817
818 /**
819 * Shared state size in bytes.
820 */
821 #define DMUB_FW_HEADER_SHARED_STATE_SIZE \
822 ((DMUB_SHARED_STATE_FEATURE__LAST + 1) * sizeof(struct dmub_shared_state_feature_block))
823
824 //==============================================================================
825 //</DMUB_STATUS>================================================================
826 //==============================================================================
827 //< DMUB_VBIOS>=================================================================
828 //==============================================================================
829
830 /*
831 * enum dmub_cmd_vbios_type - VBIOS commands.
832 *
833 * Command IDs should be treated as stable ABI.
834 * Do not reuse or modify IDs.
835 */
836 enum dmub_cmd_vbios_type {
837 /**
838 * Configures the DIG encoder.
839 */
840 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
841 /**
842 * Controls the PHY.
843 */
844 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
845 /**
846 * Sets the pixel clock/symbol clock.
847 */
848 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
849 /**
850 * Enables or disables power gating.
851 */
852 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
853 /**
854 * Controls embedded panels.
855 */
856 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
857 /**
858 * Query DP alt status on a transmitter.
859 */
860 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
861 /**
862 * Control PHY FSM
863 */
864 DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM = 29,
865 /**
866 * Controls domain power gating
867 */
868 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
869 };
870
871 //==============================================================================
872 //</DMUB_VBIOS>=================================================================
873 //==============================================================================
874 //< DMUB_GPINT>=================================================================
875 //==============================================================================
876
877 /**
878 * The shifts and masks below may alternatively be used to format and read
879 * the command register bits.
880 */
881
882 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
883 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
884
885 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
886 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
887
888 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
889 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
890
891 /**
892 * Command responses.
893 */
894
895 /**
896 * Return response for DMUB_GPINT__STOP_FW command.
897 */
898 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
899
900 /**
901 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
902 */
903 union dmub_gpint_data_register {
904 struct {
905 uint32_t param : 16; /**< 16-bit parameter */
906 uint32_t command_code : 12; /**< GPINT command */
907 uint32_t status : 4; /**< Command status bit */
908 } bits; /**< GPINT bit access */
909 uint32_t all; /**< GPINT 32-bit access */
910 };
911
912 /*
913 * enum dmub_gpint_command - GPINT command to DMCUB FW
914 *
915 * Command IDs should be treated as stable ABI.
916 * Do not reuse or modify IDs.
917 */
918 enum dmub_gpint_command {
919 /**
920 * Invalid command, ignored.
921 */
922 DMUB_GPINT__INVALID_COMMAND = 0,
923 /**
924 * DESC: Queries the firmware version.
925 * RETURN: Firmware version.
926 */
927 DMUB_GPINT__GET_FW_VERSION = 1,
928 /**
929 * DESC: Halts the firmware.
930 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
931 */
932 DMUB_GPINT__STOP_FW = 2,
933 /**
934 * DESC: Get PSR state from FW.
935 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
936 */
937 DMUB_GPINT__GET_PSR_STATE = 7,
938 /**
939 * DESC: Notifies DMCUB of the currently active streams.
940 * ARGS: Stream mask, 1 bit per active stream index.
941 */
942 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
943 /**
944 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
945 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
946 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
947 * RETURN: PSR residency in milli-percent.
948 */
949 DMUB_GPINT__PSR_RESIDENCY = 9,
950
951 /**
952 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
953 */
954 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
955
956 /**
957 * DESC: Get REPLAY state from FW.
958 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
959 */
960 DMUB_GPINT__GET_REPLAY_STATE = 13,
961
962 /**
963 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
964 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
965 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
966 * RETURN: REPLAY residency in milli-percent.
967 */
968 DMUB_GPINT__REPLAY_RESIDENCY = 14,
969
970 /**
971 * DESC: Copy bounding box to the host.
972 * ARGS: Version of bounding box to copy
973 * RETURN: Result of copying bounding box
974 */
975 DMUB_GPINT__BB_COPY = 96,
976
977 /**
978 * DESC: Updates the host addresses bit48~bit63 for bounding box.
979 * ARGS: The word3 for the 64 bit address
980 */
981 DMUB_GPINT__SET_BB_ADDR_WORD3 = 97,
982
983 /**
984 * DESC: Updates the host addresses bit32~bit47 for bounding box.
985 * ARGS: The word2 for the 64 bit address
986 */
987 DMUB_GPINT__SET_BB_ADDR_WORD2 = 98,
988
989 /**
990 * DESC: Updates the host addresses bit16~bit31 for bounding box.
991 * ARGS: The word1 for the 64 bit address
992 */
993 DMUB_GPINT__SET_BB_ADDR_WORD1 = 99,
994
995 /**
996 * DESC: Updates the host addresses bit0~bit15 for bounding box.
997 * ARGS: The word0 for the 64 bit address
998 */
999 DMUB_GPINT__SET_BB_ADDR_WORD0 = 100,
1000
1001 /**
1002 * DESC: Updates the trace buffer lower 32-bit mask.
1003 * ARGS: The new mask
1004 * RETURN: Lower 32-bit mask.
1005 */
1006 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
1007
1008 /**
1009 * DESC: Updates the trace buffer mask bit0~bit15.
1010 * ARGS: The new mask
1011 * RETURN: Lower 32-bit mask.
1012 */
1013 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
1014
1015 /**
1016 * DESC: Updates the trace buffer mask bit16~bit31.
1017 * ARGS: The new mask
1018 * RETURN: Lower 32-bit mask.
1019 */
1020 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
1021
1022 /**
1023 * DESC: Updates the trace buffer mask bit32~bit47.
1024 * ARGS: The new mask
1025 * RETURN: Lower 32-bit mask.
1026 */
1027 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2 = 114,
1028
1029 /**
1030 * DESC: Updates the trace buffer mask bit48~bit63.
1031 * ARGS: The new mask
1032 * RETURN: Lower 32-bit mask.
1033 */
1034 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3 = 115,
1035
1036 /**
1037 * DESC: Read the trace buffer mask bi0~bit15.
1038 */
1039 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0 = 116,
1040
1041 /**
1042 * DESC: Read the trace buffer mask bit16~bit31.
1043 */
1044 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD1 = 117,
1045
1046 /**
1047 * DESC: Read the trace buffer mask bi32~bit47.
1048 */
1049 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD2 = 118,
1050
1051 /**
1052 * DESC: Updates the trace buffer mask bit32~bit63.
1053 */
1054 DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119,
1055
1056 /**
1057 * DESC: Enable measurements for various task duration
1058 * ARGS: 0 - Disable measurement
1059 * 1 - Enable measurement
1060 */
1061 DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123,
1062 };
1063
1064 /**
1065 * INBOX0 generic command definition
1066 */
1067 union dmub_inbox0_cmd_common {
1068 struct {
1069 uint32_t command_code: 8; /**< INBOX0 command code */
1070 uint32_t param: 24; /**< 24-bit parameter */
1071 } bits;
1072 uint32_t all;
1073 };
1074
1075 /**
1076 * INBOX0 hw_lock command definition
1077 */
1078 union dmub_inbox0_cmd_lock_hw {
1079 struct {
1080 uint32_t command_code: 8;
1081
1082 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
1083 uint32_t hw_lock_client: 2;
1084
1085 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
1086 uint32_t otg_inst: 3;
1087 uint32_t opp_inst: 3;
1088 uint32_t dig_inst: 3;
1089
1090 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
1091 uint32_t lock_pipe: 1;
1092 uint32_t lock_cursor: 1;
1093 uint32_t lock_dig: 1;
1094 uint32_t triple_buffer_lock: 1;
1095
1096 uint32_t lock: 1; /**< Lock */
1097 uint32_t should_release: 1; /**< Release */
1098 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
1099 } bits;
1100 uint32_t all;
1101 };
1102
1103 union dmub_inbox0_data_register {
1104 union dmub_inbox0_cmd_common inbox0_cmd_common;
1105 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
1106 };
1107
1108 enum dmub_inbox0_command {
1109 /**
1110 * DESC: Invalid command, ignored.
1111 */
1112 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
1113 /**
1114 * DESC: Notification to acquire/release HW lock
1115 * ARGS:
1116 */
1117 DMUB_INBOX0_CMD__HW_LOCK = 1,
1118 };
1119 //==============================================================================
1120 //</DMUB_GPINT>=================================================================
1121 //==============================================================================
1122 //< DMUB_CMD>===================================================================
1123 //==============================================================================
1124
1125 /**
1126 * Size in bytes of each DMUB command.
1127 */
1128 #define DMUB_RB_CMD_SIZE 64
1129
1130 /**
1131 * Maximum number of items in the DMUB ringbuffer.
1132 */
1133 #define DMUB_RB_MAX_ENTRY 128
1134
1135 /**
1136 * Ringbuffer size in bytes.
1137 */
1138 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
1139
1140 /**
1141 * REG_SET mask for reg offload.
1142 */
1143 #define REG_SET_MASK 0xFFFF
1144
1145 /*
1146 * enum dmub_cmd_type - DMUB inbox command.
1147 *
1148 * Command IDs should be treated as stable ABI.
1149 * Do not reuse or modify IDs.
1150 */
1151 enum dmub_cmd_type {
1152 /**
1153 * Invalid command.
1154 */
1155 DMUB_CMD__NULL = 0,
1156 /**
1157 * Read modify write register sequence offload.
1158 */
1159 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
1160 /**
1161 * Field update register sequence offload.
1162 */
1163 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
1164 /**
1165 * Burst write sequence offload.
1166 */
1167 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
1168 /**
1169 * Reg wait sequence offload.
1170 */
1171 DMUB_CMD__REG_REG_WAIT = 4,
1172 /**
1173 * Workaround to avoid HUBP underflow during NV12 playback.
1174 */
1175 DMUB_CMD__PLAT_54186_WA = 5,
1176 /**
1177 * Command type used to query FW feature caps.
1178 */
1179 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
1180 /**
1181 * Command type used to get visual confirm color.
1182 */
1183 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
1184 /**
1185 * Command type used for all PSR commands.
1186 */
1187 DMUB_CMD__PSR = 64,
1188 /**
1189 * Command type used for all MALL commands.
1190 */
1191 DMUB_CMD__MALL = 65,
1192 /**
1193 * Command type used for all ABM commands.
1194 */
1195 DMUB_CMD__ABM = 66,
1196 /**
1197 * Command type used to update dirty rects in FW.
1198 */
1199 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
1200 /**
1201 * Command type used to update cursor info in FW.
1202 */
1203 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
1204 /**
1205 * Command type used for HW locking in FW.
1206 */
1207 DMUB_CMD__HW_LOCK = 69,
1208 /**
1209 * Command type used to access DP AUX.
1210 */
1211 DMUB_CMD__DP_AUX_ACCESS = 70,
1212 /**
1213 * Command type used for OUTBOX1 notification enable
1214 */
1215 DMUB_CMD__OUTBOX1_ENABLE = 71,
1216
1217 /**
1218 * Command type used for all idle optimization commands.
1219 */
1220 DMUB_CMD__IDLE_OPT = 72,
1221 /**
1222 * Command type used for all clock manager commands.
1223 */
1224 DMUB_CMD__CLK_MGR = 73,
1225 /**
1226 * Command type used for all panel control commands.
1227 */
1228 DMUB_CMD__PANEL_CNTL = 74,
1229
1230 /**
1231 * Command type used for all CAB commands.
1232 */
1233 DMUB_CMD__CAB_FOR_SS = 75,
1234
1235 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
1236
1237 /**
1238 * Command type used for interfacing with DPIA.
1239 */
1240 DMUB_CMD__DPIA = 77,
1241 /**
1242 * Command type used for EDID CEA parsing
1243 */
1244 DMUB_CMD__EDID_CEA = 79,
1245 /**
1246 * Command type used for getting usbc cable ID
1247 */
1248 DMUB_CMD_GET_USBC_CABLE_ID = 81,
1249 /**
1250 * Command type used to query HPD state.
1251 */
1252 DMUB_CMD__QUERY_HPD_STATE = 82,
1253 /**
1254 * Command type used for all VBIOS interface commands.
1255 */
1256 /**
1257 * Command type used for all REPLAY commands.
1258 */
1259 DMUB_CMD__REPLAY = 83,
1260
1261 /**
1262 * Command type used for all SECURE_DISPLAY commands.
1263 */
1264 DMUB_CMD__SECURE_DISPLAY = 85,
1265
1266 /**
1267 * Command type used to set DPIA HPD interrupt state
1268 */
1269 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1270
1271 /**
1272 * Command type used for all PSP commands.
1273 */
1274 DMUB_CMD__PSP = 88,
1275
1276 DMUB_CMD__VBIOS = 128,
1277 };
1278
1279 /**
1280 * enum dmub_out_cmd_type - DMUB outbox commands.
1281 */
1282 enum dmub_out_cmd_type {
1283 /**
1284 * Invalid outbox command, ignored.
1285 */
1286 DMUB_OUT_CMD__NULL = 0,
1287 /**
1288 * Command type used for DP AUX Reply data notification
1289 */
1290 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1291 /**
1292 * Command type used for DP HPD event notification
1293 */
1294 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1295 /**
1296 * Command type used for SET_CONFIG Reply notification
1297 */
1298 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1299 /**
1300 * Command type used for USB4 DPIA notification
1301 */
1302 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1303 /**
1304 * Command type used for HPD redetect notification
1305 */
1306 DMUB_OUT_CMD__HPD_SENSE_NOTIFY = 6,
1307 };
1308
1309 /* DMUB_CMD__DPIA command sub-types. */
1310 enum dmub_cmd_dpia_type {
1311 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1312 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
1313 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1314 DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3,
1315 };
1316
1317 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1318 enum dmub_cmd_dpia_notification_type {
1319 DPIA_NOTIFY__BW_ALLOCATION = 0,
1320 };
1321
1322 #pragma pack(push, 1)
1323
1324 /**
1325 * struct dmub_cmd_header - Common command header fields.
1326 */
1327 struct dmub_cmd_header {
1328 unsigned int type : 8; /**< command type */
1329 unsigned int sub_type : 8; /**< command sub type */
1330 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1331 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1332 unsigned int reserved0 : 6; /**< reserved bits */
1333 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1334 unsigned int reserved1 : 2; /**< reserved bits */
1335 };
1336
1337 /*
1338 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1339 *
1340 * 60 payload bytes can hold up to 5 sets of read modify writes,
1341 * each take 3 dwords.
1342 *
1343 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1344 *
1345 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1346 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1347 */
1348 struct dmub_cmd_read_modify_write_sequence {
1349 uint32_t addr; /**< register address */
1350 uint32_t modify_mask; /**< modify mask */
1351 uint32_t modify_value; /**< modify value */
1352 };
1353
1354 /**
1355 * Maximum number of ops in read modify write sequence.
1356 */
1357 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1358
1359 /**
1360 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1361 */
1362 struct dmub_rb_cmd_read_modify_write {
1363 struct dmub_cmd_header header; /**< command header */
1364 /**
1365 * Read modify write sequence.
1366 */
1367 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
1368 };
1369
1370 /*
1371 * Update a register with specified masks and values sequeunce
1372 *
1373 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
1374 *
1375 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
1376 *
1377 *
1378 * USE CASE:
1379 * 1. auto-increment register where additional read would update pointer and produce wrong result
1380 * 2. toggle a bit without read in the middle
1381 */
1382
1383 struct dmub_cmd_reg_field_update_sequence {
1384 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1385 uint32_t modify_value; /**< value to update with */
1386 };
1387
1388 /**
1389 * Maximum number of ops in field update sequence.
1390 */
1391 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1392
1393 /**
1394 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1395 */
1396 struct dmub_rb_cmd_reg_field_update_sequence {
1397 struct dmub_cmd_header header; /**< command header */
1398 uint32_t addr; /**< register address */
1399 /**
1400 * Field update sequence.
1401 */
1402 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
1403 };
1404
1405
1406 /**
1407 * Maximum number of burst write values.
1408 */
1409 #define DMUB_BURST_WRITE_VALUES__MAX 14
1410
1411 /*
1412 * struct dmub_rb_cmd_burst_write - Burst write
1413 *
1414 * support use case such as writing out LUTs.
1415 *
1416 * 60 payload bytes can hold up to 14 values to write to given address
1417 *
1418 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
1419 */
1420 struct dmub_rb_cmd_burst_write {
1421 struct dmub_cmd_header header; /**< command header */
1422 uint32_t addr; /**< register start address */
1423 /**
1424 * Burst write register values.
1425 */
1426 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
1427 };
1428
1429 /**
1430 * struct dmub_rb_cmd_common - Common command header
1431 */
1432 struct dmub_rb_cmd_common {
1433 struct dmub_cmd_header header; /**< command header */
1434 /**
1435 * Padding to RB_CMD_SIZE
1436 */
1437 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1438 };
1439
1440 /**
1441 * struct dmub_cmd_reg_wait_data - Register wait data
1442 */
1443 struct dmub_cmd_reg_wait_data {
1444 uint32_t addr; /**< Register address */
1445 uint32_t mask; /**< Mask for register bits */
1446 uint32_t condition_field_value; /**< Value to wait for */
1447 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
1448 };
1449
1450 /**
1451 * struct dmub_rb_cmd_reg_wait - Register wait command
1452 */
1453 struct dmub_rb_cmd_reg_wait {
1454 struct dmub_cmd_header header; /**< Command header */
1455 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
1456 };
1457
1458 /**
1459 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1460 *
1461 * Reprograms surface parameters to avoid underflow.
1462 */
1463 struct dmub_cmd_PLAT_54186_wa {
1464 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1465 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1466 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1467 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1468 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
1469 struct {
1470 uint32_t hubp_inst : 4; /**< HUBP instance */
1471 uint32_t tmz_surface : 1; /**< TMZ enable or disable */
1472 uint32_t immediate :1; /**< Immediate flip */
1473 uint32_t vmid : 4; /**< VMID */
1474 uint32_t grph_stereo : 1; /**< 1 if stereo */
1475 uint32_t reserved : 21; /**< Reserved */
1476 } flip_params; /**< Pageflip parameters */
1477 uint32_t reserved[9]; /**< Reserved bits */
1478 };
1479
1480 /**
1481 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1482 */
1483 struct dmub_rb_cmd_PLAT_54186_wa {
1484 struct dmub_cmd_header header; /**< Command header */
1485 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
1486 };
1487
1488 /**
1489 * enum dmub_cmd_mall_type - MALL commands
1490 */
1491 enum dmub_cmd_mall_type {
1492 /**
1493 * Allows display refresh from MALL.
1494 */
1495 DMUB_CMD__MALL_ACTION_ALLOW = 0,
1496 /**
1497 * Disallows display refresh from MALL.
1498 */
1499 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
1500 /**
1501 * Cursor copy for MALL.
1502 */
1503 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
1504 /**
1505 * Controls DF requests.
1506 */
1507 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
1508 };
1509
1510 /**
1511 * struct dmub_rb_cmd_mall - MALL command data.
1512 */
1513 struct dmub_rb_cmd_mall {
1514 struct dmub_cmd_header header; /**< Common command header */
1515 union dmub_addr cursor_copy_src; /**< Cursor copy address */
1516 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1517 uint32_t tmr_delay; /**< Timer delay */
1518 uint32_t tmr_scale; /**< Timer scale */
1519 uint16_t cursor_width; /**< Cursor width in pixels */
1520 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1521 uint16_t cursor_height; /**< Cursor height in pixels */
1522 uint8_t cursor_bpp; /**< Cursor bits per pixel */
1523 uint8_t debug_bits; /**< Debug bits */
1524
1525 uint8_t reserved1; /**< Reserved bits */
1526 uint8_t reserved2; /**< Reserved bits */
1527 };
1528
1529 /**
1530 * enum dmub_cmd_cab_type - CAB command data.
1531 */
1532 enum dmub_cmd_cab_type {
1533 /**
1534 * No idle optimizations (i.e. no CAB)
1535 */
1536 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1537 /**
1538 * No DCN requests for memory
1539 */
1540 DMUB_CMD__CAB_NO_DCN_REQ = 1,
1541 /**
1542 * Fit surfaces in CAB (i.e. CAB enable)
1543 */
1544 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1545 /**
1546 * Do not fit surfaces in CAB (i.e. no CAB)
1547 */
1548 DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB = 3,
1549 };
1550
1551 /**
1552 * struct dmub_rb_cmd_cab - CAB command data.
1553 */
1554 struct dmub_rb_cmd_cab_for_ss {
1555 struct dmub_cmd_header header;
1556 uint8_t cab_alloc_ways; /* total number of ways */
1557 uint8_t debug_bits; /* debug bits */
1558 };
1559
1560 /**
1561 * Enum for indicating which MCLK switch mode per pipe
1562 */
1563 enum mclk_switch_mode {
1564 NONE = 0,
1565 FPO = 1,
1566 SUBVP = 2,
1567 VBLANK = 3,
1568 };
1569
1570 /* Per pipe struct which stores the MCLK switch mode
1571 * data to be sent to DMUB.
1572 * Named "v2" for now -- once FPO and SUBVP are fully merged
1573 * the type name can be updated
1574 */
1575 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
1576 union {
1577 struct {
1578 uint32_t pix_clk_100hz;
1579 uint16_t main_vblank_start;
1580 uint16_t main_vblank_end;
1581 uint16_t mall_region_lines;
1582 uint16_t prefetch_lines;
1583 uint16_t prefetch_to_mall_start_lines;
1584 uint16_t processing_delay_lines;
1585 uint16_t htotal; // required to calculate line time for multi-display cases
1586 uint16_t vtotal;
1587 uint8_t main_pipe_index;
1588 uint8_t phantom_pipe_index;
1589 /* Since the microschedule is calculated in terms of OTG lines,
1590 * include any scaling factors to make sure when we get accurate
1591 * conversion when programming MALL_START_LINE (which is in terms
1592 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1593 * is 1/2 (numerator = 1, denominator = 2).
1594 */
1595 uint8_t scale_factor_numerator;
1596 uint8_t scale_factor_denominator;
1597 uint8_t is_drr;
1598 uint8_t main_split_pipe_index;
1599 uint8_t phantom_split_pipe_index;
1600 } subvp_data;
1601
1602 struct {
1603 uint32_t pix_clk_100hz;
1604 uint16_t vblank_start;
1605 uint16_t vblank_end;
1606 uint16_t vstartup_start;
1607 uint16_t vtotal;
1608 uint16_t htotal;
1609 uint8_t vblank_pipe_index;
1610 uint8_t padding[1];
1611 struct {
1612 uint8_t drr_in_use;
1613 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1614 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1615 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1616 uint8_t use_ramping; // Use ramping or not
1617 uint8_t drr_vblank_start_margin;
1618 } drr_info; // DRR considered as part of SubVP + VBLANK case
1619 } vblank_data;
1620 } pipe_config;
1621
1622 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1623 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1624 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1625 */
1626 uint8_t mode; // enum mclk_switch_mode
1627 };
1628
1629 /**
1630 * Config data for Sub-VP and FPO
1631 * Named "v2" for now -- once FPO and SUBVP are fully merged
1632 * the type name can be updated
1633 */
1634 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1635 uint16_t watermark_a_cache;
1636 uint8_t vertical_int_margin_us;
1637 uint8_t pstate_allow_width_us;
1638 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1639 };
1640
1641 /**
1642 * DMUB rb command definition for Sub-VP and FPO
1643 * Named "v2" for now -- once FPO and SUBVP are fully merged
1644 * the type name can be updated
1645 */
1646 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1647 struct dmub_cmd_header header;
1648 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1649 };
1650
1651 struct dmub_flip_addr_info {
1652 uint32_t surf_addr_lo;
1653 uint32_t surf_addr_c_lo;
1654 uint32_t meta_addr_lo;
1655 uint32_t meta_addr_c_lo;
1656 uint16_t surf_addr_hi;
1657 uint16_t surf_addr_c_hi;
1658 uint16_t meta_addr_hi;
1659 uint16_t meta_addr_c_hi;
1660 };
1661
1662 struct dmub_fams2_flip_info {
1663 union {
1664 struct {
1665 uint8_t is_immediate: 1;
1666 } bits;
1667 uint8_t all;
1668 } config;
1669 uint8_t otg_inst;
1670 uint8_t pipe_mask;
1671 uint8_t pad;
1672 struct dmub_flip_addr_info addr_info;
1673 };
1674
1675 struct dmub_rb_cmd_fams2_flip {
1676 struct dmub_cmd_header header;
1677 struct dmub_fams2_flip_info flip_info;
1678 };
1679
1680 struct dmub_optc_state_v2 {
1681 uint32_t v_total_min;
1682 uint32_t v_total_max;
1683 uint32_t v_total_mid;
1684 uint32_t v_total_mid_frame_num;
1685 uint8_t program_manual_trigger;
1686 uint8_t tg_inst;
1687 uint8_t pad[2];
1688 };
1689
1690 struct dmub_optc_position {
1691 uint32_t vpos;
1692 uint32_t hpos;
1693 uint32_t frame;
1694 };
1695
1696 struct dmub_rb_cmd_fams2_drr_update {
1697 struct dmub_cmd_header header;
1698 struct dmub_optc_state_v2 dmub_optc_state_req;
1699 };
1700
1701 /* HW and FW global configuration data for FAMS2 */
1702 /* FAMS2 types and structs */
1703 enum fams2_stream_type {
1704 FAMS2_STREAM_TYPE_NONE = 0,
1705 FAMS2_STREAM_TYPE_VBLANK = 1,
1706 FAMS2_STREAM_TYPE_VACTIVE = 2,
1707 FAMS2_STREAM_TYPE_DRR = 3,
1708 FAMS2_STREAM_TYPE_SUBVP = 4,
1709 };
1710
1711 /* dynamic stream state */
1712 struct dmub_fams2_legacy_stream_dynamic_state {
1713 uint8_t force_allow_at_vblank;
1714 uint8_t pad[3];
1715 };
1716
1717 struct dmub_fams2_subvp_stream_dynamic_state {
1718 uint16_t viewport_start_hubp_vline;
1719 uint16_t viewport_height_hubp_vlines;
1720 uint16_t viewport_start_c_hubp_vline;
1721 uint16_t viewport_height_c_hubp_vlines;
1722 uint16_t phantom_viewport_height_hubp_vlines;
1723 uint16_t phantom_viewport_height_c_hubp_vlines;
1724 uint16_t microschedule_start_otg_vline;
1725 uint16_t mall_start_otg_vline;
1726 uint16_t mall_start_hubp_vline;
1727 uint16_t mall_start_c_hubp_vline;
1728 uint8_t force_allow_at_vblank_only;
1729 uint8_t pad[3];
1730 };
1731
1732 struct dmub_fams2_drr_stream_dynamic_state {
1733 uint16_t stretched_vtotal;
1734 uint8_t use_cur_vtotal;
1735 uint8_t pad;
1736 };
1737
1738 struct dmub_fams2_stream_dynamic_state {
1739 uint64_t ref_tick;
1740 uint32_t cur_vtotal;
1741 uint16_t adjusted_allow_end_otg_vline;
1742 uint8_t pad[2];
1743 struct dmub_optc_position ref_otg_pos;
1744 struct dmub_optc_position target_otg_pos;
1745 union {
1746 struct dmub_fams2_legacy_stream_dynamic_state legacy;
1747 struct dmub_fams2_subvp_stream_dynamic_state subvp;
1748 struct dmub_fams2_drr_stream_dynamic_state drr;
1749 } sub_state;
1750 };
1751
1752 /* static stream state */
1753 struct dmub_fams2_legacy_stream_static_state {
1754 uint8_t vactive_det_fill_delay_otg_vlines;
1755 uint8_t programming_delay_otg_vlines;
1756 };
1757
1758 struct dmub_fams2_subvp_stream_static_state {
1759 uint16_t vratio_numerator;
1760 uint16_t vratio_denominator;
1761 uint16_t phantom_vtotal;
1762 uint16_t phantom_vactive;
1763 union {
1764 struct {
1765 uint8_t is_multi_planar : 1;
1766 uint8_t is_yuv420 : 1;
1767 } bits;
1768 uint8_t all;
1769 } config;
1770 uint8_t programming_delay_otg_vlines;
1771 uint8_t prefetch_to_mall_otg_vlines;
1772 uint8_t phantom_otg_inst;
1773 uint8_t phantom_pipe_mask;
1774 uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough)
1775 };
1776
1777 struct dmub_fams2_drr_stream_static_state {
1778 uint16_t nom_stretched_vtotal;
1779 uint8_t programming_delay_otg_vlines;
1780 uint8_t only_stretch_if_required;
1781 uint8_t pad[2];
1782 };
1783
1784 struct dmub_fams2_stream_static_state {
1785 enum fams2_stream_type type;
1786 uint32_t otg_vline_time_ns;
1787 uint32_t otg_vline_time_ticks;
1788 uint16_t htotal;
1789 uint16_t vtotal; // nominal vtotal
1790 uint16_t vblank_start;
1791 uint16_t vblank_end;
1792 uint16_t max_vtotal;
1793 uint16_t allow_start_otg_vline;
1794 uint16_t allow_end_otg_vline;
1795 uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed
1796 uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start
1797 uint8_t contention_delay_otg_vlines; // time to budget for contention on execution
1798 uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing
1799 uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline
1800 union {
1801 struct {
1802 uint8_t is_drr: 1; // stream is DRR enabled
1803 uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal
1804 uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank
1805 } bits;
1806 uint8_t all;
1807 } config;
1808 uint8_t otg_inst;
1809 uint8_t pipe_mask; // pipe mask for the whole config
1810 uint8_t num_planes;
1811 uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough)
1812 uint8_t pad[DMUB_MAX_PLANES % 4];
1813 union {
1814 struct dmub_fams2_legacy_stream_static_state legacy;
1815 struct dmub_fams2_subvp_stream_static_state subvp;
1816 struct dmub_fams2_drr_stream_static_state drr;
1817 } sub_state;
1818 };
1819
1820 /**
1821 * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive
1822 * p-state request to allow latency
1823 */
1824 enum dmub_fams2_allow_delay_check_mode {
1825 /* No check for request to allow delay */
1826 FAMS2_ALLOW_DELAY_CHECK_NONE = 0,
1827 /* Check for request to allow delay */
1828 FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1,
1829 /* Check for prepare to allow delay */
1830 FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2,
1831 };
1832
1833 union dmub_fams2_global_feature_config {
1834 struct {
1835 uint32_t enable: 1;
1836 uint32_t enable_ppt_check: 1;
1837 uint32_t enable_stall_recovery: 1;
1838 uint32_t enable_debug: 1;
1839 uint32_t enable_offload_flip: 1;
1840 uint32_t enable_visual_confirm: 1;
1841 uint32_t allow_delay_check_mode: 2;
1842 uint32_t reserved: 24;
1843 } bits;
1844 uint32_t all;
1845 };
1846
1847 struct dmub_cmd_fams2_global_config {
1848 uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin
1849 uint32_t lock_wait_time_us; // time to forecast acquisition of lock
1850 uint32_t num_streams;
1851 union dmub_fams2_global_feature_config features;
1852 uint32_t recovery_timeout_us;
1853 uint32_t hwfq_flip_programming_delay_us;
1854 };
1855
1856 union dmub_cmd_fams2_config {
1857 struct dmub_cmd_fams2_global_config global;
1858 struct dmub_fams2_stream_static_state stream;
1859 };
1860
1861 /**
1862 * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy)
1863 */
1864 struct dmub_rb_cmd_fams2 {
1865 struct dmub_cmd_header header;
1866 union dmub_cmd_fams2_config config;
1867 };
1868
1869 /**
1870 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1871 */
1872 enum dmub_cmd_idle_opt_type {
1873 /**
1874 * DCN hardware restore.
1875 */
1876 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1877
1878 /**
1879 * DCN hardware save.
1880 */
1881 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
1882
1883 /**
1884 * DCN hardware notify idle.
1885 */
1886 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2,
1887
1888 /**
1889 * DCN hardware notify power state.
1890 */
1891 DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3,
1892 };
1893
1894 /**
1895 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1896 */
1897 struct dmub_rb_cmd_idle_opt_dcn_restore {
1898 struct dmub_cmd_header header; /**< header */
1899 };
1900
1901 /**
1902 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1903 */
1904 struct dmub_dcn_notify_idle_cntl_data {
1905 uint8_t driver_idle;
1906 uint8_t skip_otg_disable;
1907 uint8_t reserved[58];
1908 };
1909
1910 /**
1911 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1912 */
1913 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
1914 struct dmub_cmd_header header; /**< header */
1915 struct dmub_dcn_notify_idle_cntl_data cntl_data;
1916 };
1917
1918 /**
1919 * enum dmub_idle_opt_dc_power_state - DC power states.
1920 */
1921 enum dmub_idle_opt_dc_power_state {
1922 DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0,
1923 DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1,
1924 DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2,
1925 DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4,
1926 DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8,
1927 };
1928
1929 /**
1930 * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
1931 */
1932 struct dmub_idle_opt_set_dc_power_state_data {
1933 uint8_t power_state; /**< power state */
1934 uint8_t pad[3]; /**< padding */
1935 };
1936
1937 /**
1938 * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
1939 */
1940 struct dmub_rb_cmd_idle_opt_set_dc_power_state {
1941 struct dmub_cmd_header header; /**< header */
1942 struct dmub_idle_opt_set_dc_power_state_data data;
1943 };
1944
1945 /**
1946 * struct dmub_clocks - Clock update notification.
1947 */
1948 struct dmub_clocks {
1949 uint32_t dispclk_khz; /**< dispclk kHz */
1950 uint32_t dppclk_khz; /**< dppclk kHz */
1951 uint32_t dcfclk_khz; /**< dcfclk kHz */
1952 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1953 };
1954
1955 /**
1956 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1957 */
1958 enum dmub_cmd_clk_mgr_type {
1959 /**
1960 * Notify DMCUB of clock update.
1961 */
1962 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1963 };
1964
1965 /**
1966 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1967 */
1968 struct dmub_rb_cmd_clk_mgr_notify_clocks {
1969 struct dmub_cmd_header header; /**< header */
1970 struct dmub_clocks clocks; /**< clock data */
1971 };
1972
1973 /**
1974 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1975 */
1976 struct dmub_cmd_digx_encoder_control_data {
1977 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1978 };
1979
1980 /**
1981 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1982 */
1983 struct dmub_rb_cmd_digx_encoder_control {
1984 struct dmub_cmd_header header; /**< header */
1985 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1986 };
1987
1988 /**
1989 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1990 */
1991 struct dmub_cmd_set_pixel_clock_data {
1992 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1993 };
1994
1995 /**
1996 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1997 */
1998 struct dmub_rb_cmd_set_pixel_clock {
1999 struct dmub_cmd_header header; /**< header */
2000 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
2001 };
2002
2003 /**
2004 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
2005 */
2006 struct dmub_cmd_enable_disp_power_gating_data {
2007 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
2008 };
2009
2010 /**
2011 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
2012 */
2013 struct dmub_rb_cmd_enable_disp_power_gating {
2014 struct dmub_cmd_header header; /**< header */
2015 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
2016 };
2017
2018 /**
2019 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
2020 */
2021 struct dmub_dig_transmitter_control_data_v1_7 {
2022 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
2023 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
2024 union {
2025 uint8_t digmode; /**< enum atom_encode_mode_def */
2026 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
2027 } mode_laneset;
2028 uint8_t lanenum; /**< Number of lanes */
2029 union {
2030 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
2031 } symclk_units;
2032 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
2033 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
2034 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
2035 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
2036 uint8_t reserved1; /**< For future use */
2037 uint8_t reserved2[3]; /**< For future use */
2038 uint32_t reserved3[11]; /**< For future use */
2039 };
2040
2041 /**
2042 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
2043 */
2044 union dmub_cmd_dig1_transmitter_control_data {
2045 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
2046 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
2047 };
2048
2049 /**
2050 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
2051 */
2052 struct dmub_rb_cmd_dig1_transmitter_control {
2053 struct dmub_cmd_header header; /**< header */
2054 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
2055 };
2056
2057 /**
2058 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
2059 */
2060 struct dmub_rb_cmd_domain_control_data {
2061 uint8_t inst : 6; /**< DOMAIN instance to control */
2062 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
2063 uint8_t reserved[3]; /**< Reserved for future use */
2064 };
2065
2066 /**
2067 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
2068 */
2069 struct dmub_rb_cmd_domain_control {
2070 struct dmub_cmd_header header; /**< header */
2071 struct dmub_rb_cmd_domain_control_data data; /**< payload */
2072 };
2073
2074 /**
2075 * DPIA tunnel command parameters.
2076 */
2077 struct dmub_cmd_dig_dpia_control_data {
2078 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
2079 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
2080 union {
2081 uint8_t digmode; /** enum atom_encode_mode_def */
2082 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
2083 } mode_laneset;
2084 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
2085 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
2086 uint8_t hpdsel; /** =0: HPD is not assigned */
2087 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
2088 uint8_t dpia_id; /** Index of DPIA */
2089 uint8_t fec_rdy : 1;
2090 uint8_t reserved : 7;
2091 uint32_t reserved1;
2092 };
2093
2094 /**
2095 * DMUB command for DPIA tunnel control.
2096 */
2097 struct dmub_rb_cmd_dig1_dpia_control {
2098 struct dmub_cmd_header header;
2099 struct dmub_cmd_dig_dpia_control_data dpia_control;
2100 };
2101
2102 /**
2103 * SET_CONFIG Command Payload
2104 */
2105 struct set_config_cmd_payload {
2106 uint8_t msg_type; /* set config message type */
2107 uint8_t msg_data; /* set config message data */
2108 };
2109
2110 /**
2111 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
2112 */
2113 struct dmub_cmd_set_config_control_data {
2114 struct set_config_cmd_payload cmd_pkt;
2115 uint8_t instance; /* DPIA instance */
2116 uint8_t immed_status; /* Immediate status returned in case of error */
2117 };
2118
2119 /**
2120 * DMUB command structure for SET_CONFIG command.
2121 */
2122 struct dmub_rb_cmd_set_config_access {
2123 struct dmub_cmd_header header; /* header */
2124 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
2125 };
2126
2127 /**
2128 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
2129 */
2130 struct dmub_cmd_mst_alloc_slots_control_data {
2131 uint8_t mst_alloc_slots; /* mst slots to be allotted */
2132 uint8_t instance; /* DPIA instance */
2133 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
2134 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
2135 };
2136
2137 /**
2138 * DMUB command structure for SET_ command.
2139 */
2140 struct dmub_rb_cmd_set_mst_alloc_slots {
2141 struct dmub_cmd_header header; /* header */
2142 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
2143 };
2144
2145 /**
2146 * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command.
2147 */
2148 struct dmub_cmd_tps_notification_data {
2149 uint8_t instance; /* DPIA instance */
2150 uint8_t tps; /* requested training pattern */
2151 uint8_t reserved1;
2152 uint8_t reserved2;
2153 };
2154
2155 /**
2156 * DMUB command structure for SET_TPS_NOTIFICATION command.
2157 */
2158 struct dmub_rb_cmd_set_tps_notification {
2159 struct dmub_cmd_header header; /* header */
2160 struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */
2161 };
2162
2163 /**
2164 * DMUB command structure for DPIA HPD int enable control.
2165 */
2166 struct dmub_rb_cmd_dpia_hpd_int_enable {
2167 struct dmub_cmd_header header; /* header */
2168 uint32_t enable; /* dpia hpd interrupt enable */
2169 };
2170
2171 /**
2172 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
2173 */
2174 struct dmub_rb_cmd_dpphy_init {
2175 struct dmub_cmd_header header; /**< header */
2176 uint8_t reserved[60]; /**< reserved bits */
2177 };
2178
2179 /**
2180 * enum dp_aux_request_action - DP AUX request command listing.
2181 *
2182 * 4 AUX request command bits are shifted to high nibble.
2183 */
2184 enum dp_aux_request_action {
2185 /** I2C-over-AUX write request */
2186 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
2187 /** I2C-over-AUX read request */
2188 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
2189 /** I2C-over-AUX write status request */
2190 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
2191 /** I2C-over-AUX write request with MOT=1 */
2192 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
2193 /** I2C-over-AUX read request with MOT=1 */
2194 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
2195 /** I2C-over-AUX write status request with MOT=1 */
2196 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
2197 /** Native AUX write request */
2198 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
2199 /** Native AUX read request */
2200 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
2201 };
2202
2203 /**
2204 * enum aux_return_code_type - DP AUX process return code listing.
2205 */
2206 enum aux_return_code_type {
2207 /** AUX process succeeded */
2208 AUX_RET_SUCCESS = 0,
2209 /** AUX process failed with unknown reason */
2210 AUX_RET_ERROR_UNKNOWN,
2211 /** AUX process completed with invalid reply */
2212 AUX_RET_ERROR_INVALID_REPLY,
2213 /** AUX process timed out */
2214 AUX_RET_ERROR_TIMEOUT,
2215 /** HPD was low during AUX process */
2216 AUX_RET_ERROR_HPD_DISCON,
2217 /** Failed to acquire AUX engine */
2218 AUX_RET_ERROR_ENGINE_ACQUIRE,
2219 /** AUX request not supported */
2220 AUX_RET_ERROR_INVALID_OPERATION,
2221 /** AUX process not available */
2222 AUX_RET_ERROR_PROTOCOL_ERROR,
2223 };
2224
2225 /**
2226 * enum aux_channel_type - DP AUX channel type listing.
2227 */
2228 enum aux_channel_type {
2229 /** AUX thru Legacy DP AUX */
2230 AUX_CHANNEL_LEGACY_DDC,
2231 /** AUX thru DPIA DP tunneling */
2232 AUX_CHANNEL_DPIA
2233 };
2234
2235 /**
2236 * struct aux_transaction_parameters - DP AUX request transaction data
2237 */
2238 struct aux_transaction_parameters {
2239 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
2240 uint8_t action; /**< enum dp_aux_request_action */
2241 uint8_t length; /**< DP AUX request data length */
2242 uint8_t reserved; /**< For future use */
2243 uint32_t address; /**< DP AUX address */
2244 uint8_t data[16]; /**< DP AUX write data */
2245 };
2246
2247 /**
2248 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
2249 */
2250 struct dmub_cmd_dp_aux_control_data {
2251 uint8_t instance; /**< AUX instance or DPIA instance */
2252 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
2253 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
2254 uint8_t reserved0; /**< For future use */
2255 uint16_t timeout; /**< timeout time in us */
2256 uint16_t reserved1; /**< For future use */
2257 enum aux_channel_type type; /**< enum aux_channel_type */
2258 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
2259 };
2260
2261 /**
2262 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
2263 */
2264 struct dmub_rb_cmd_dp_aux_access {
2265 /**
2266 * Command header.
2267 */
2268 struct dmub_cmd_header header;
2269 /**
2270 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
2271 */
2272 struct dmub_cmd_dp_aux_control_data aux_control;
2273 };
2274
2275 /**
2276 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
2277 */
2278 struct dmub_rb_cmd_outbox1_enable {
2279 /**
2280 * Command header.
2281 */
2282 struct dmub_cmd_header header;
2283 /**
2284 * enable: 0x0 -> disable outbox1 notification (default value)
2285 * 0x1 -> enable outbox1 notification
2286 */
2287 uint32_t enable;
2288 };
2289
2290 /* DP AUX Reply command - OutBox Cmd */
2291 /**
2292 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2293 */
2294 struct aux_reply_data {
2295 /**
2296 * Aux cmd
2297 */
2298 uint8_t command;
2299 /**
2300 * Aux reply data length (max: 16 bytes)
2301 */
2302 uint8_t length;
2303 /**
2304 * Alignment only
2305 */
2306 uint8_t pad[2];
2307 /**
2308 * Aux reply data
2309 */
2310 uint8_t data[16];
2311 };
2312
2313 /**
2314 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2315 */
2316 struct aux_reply_control_data {
2317 /**
2318 * Reserved for future use
2319 */
2320 uint32_t handle;
2321 /**
2322 * Aux Instance
2323 */
2324 uint8_t instance;
2325 /**
2326 * Aux transaction result: definition in enum aux_return_code_type
2327 */
2328 uint8_t result;
2329 /**
2330 * Alignment only
2331 */
2332 uint16_t pad;
2333 };
2334
2335 /**
2336 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
2337 */
2338 struct dmub_rb_cmd_dp_aux_reply {
2339 /**
2340 * Command header.
2341 */
2342 struct dmub_cmd_header header;
2343 /**
2344 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2345 */
2346 struct aux_reply_control_data control;
2347 /**
2348 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
2349 */
2350 struct aux_reply_data reply_data;
2351 };
2352
2353 /* DP HPD Notify command - OutBox Cmd */
2354 /**
2355 * DP HPD Type
2356 */
2357 enum dp_hpd_type {
2358 /**
2359 * Normal DP HPD
2360 */
2361 DP_HPD = 0,
2362 /**
2363 * DP HPD short pulse
2364 */
2365 DP_IRQ
2366 };
2367
2368 /**
2369 * DP HPD Status
2370 */
2371 enum dp_hpd_status {
2372 /**
2373 * DP_HPD status low
2374 */
2375 DP_HPD_UNPLUG = 0,
2376 /**
2377 * DP_HPD status high
2378 */
2379 DP_HPD_PLUG
2380 };
2381
2382 /**
2383 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2384 */
2385 struct dp_hpd_data {
2386 /**
2387 * DP HPD instance
2388 */
2389 uint8_t instance;
2390 /**
2391 * HPD type
2392 */
2393 uint8_t hpd_type;
2394 /**
2395 * HPD status: only for type: DP_HPD to indicate status
2396 */
2397 uint8_t hpd_status;
2398 /**
2399 * Alignment only
2400 */
2401 uint8_t pad;
2402 };
2403
2404 /**
2405 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2406 */
2407 struct dmub_rb_cmd_dp_hpd_notify {
2408 /**
2409 * Command header.
2410 */
2411 struct dmub_cmd_header header;
2412 /**
2413 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
2414 */
2415 struct dp_hpd_data hpd_data;
2416 };
2417
2418 /**
2419 * Definition of a SET_CONFIG reply from DPOA.
2420 */
2421 enum set_config_status {
2422 SET_CONFIG_PENDING = 0,
2423 SET_CONFIG_ACK_RECEIVED,
2424 SET_CONFIG_RX_TIMEOUT,
2425 SET_CONFIG_UNKNOWN_ERROR,
2426 };
2427
2428 /**
2429 * Definition of a set_config reply
2430 */
2431 struct set_config_reply_control_data {
2432 uint8_t instance; /* DPIA Instance */
2433 uint8_t status; /* Set Config reply */
2434 uint16_t pad; /* Alignment */
2435 };
2436
2437 /**
2438 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
2439 */
2440 struct dmub_rb_cmd_dp_set_config_reply {
2441 struct dmub_cmd_header header;
2442 struct set_config_reply_control_data set_config_reply_control;
2443 };
2444
2445 /**
2446 * Definition of a DPIA notification header
2447 */
2448 struct dpia_notification_header {
2449 uint8_t instance; /**< DPIA Instance */
2450 uint8_t reserved[3];
2451 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
2452 };
2453
2454 /**
2455 * Definition of the common data struct of DPIA notification
2456 */
2457 struct dpia_notification_common {
2458 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
2459 - sizeof(struct dpia_notification_header)];
2460 };
2461
2462 /**
2463 * Definition of a DPIA notification data
2464 */
2465 struct dpia_bw_allocation_notify_data {
2466 union {
2467 struct {
2468 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
2469 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
2470 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
2471 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
2472 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
2473 uint16_t reserved: 11; /**< Reserved */
2474 } bits;
2475
2476 uint16_t flags;
2477 };
2478
2479 uint8_t cm_id; /**< CM ID */
2480 uint8_t group_id; /**< Group ID */
2481 uint8_t granularity; /**< BW Allocation Granularity */
2482 uint8_t estimated_bw; /**< Estimated_BW */
2483 uint8_t allocated_bw; /**< Allocated_BW */
2484 uint8_t reserved;
2485 };
2486
2487 /**
2488 * union dpia_notify_data_type - DPIA Notification in Outbox command
2489 */
2490 union dpia_notification_data {
2491 /**
2492 * DPIA Notification for common data struct
2493 */
2494 struct dpia_notification_common common_data;
2495
2496 /**
2497 * DPIA Notification for DP BW Allocation support
2498 */
2499 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
2500 };
2501
2502 /**
2503 * Definition of a DPIA notification payload
2504 */
2505 struct dpia_notification_payload {
2506 struct dpia_notification_header header;
2507 union dpia_notification_data data; /**< DPIA notification payload data */
2508 };
2509
2510 /**
2511 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
2512 */
2513 struct dmub_rb_cmd_dpia_notification {
2514 struct dmub_cmd_header header; /**< DPIA notification header */
2515 struct dpia_notification_payload payload; /**< DPIA notification payload */
2516 };
2517
2518 /**
2519 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2520 */
2521 struct dmub_cmd_hpd_state_query_data {
2522 uint8_t instance; /**< HPD instance or DPIA instance */
2523 uint8_t result; /**< For returning HPD state */
2524 uint16_t pad; /** < Alignment */
2525 enum aux_channel_type ch_type; /**< enum aux_channel_type */
2526 enum aux_return_code_type status; /**< for returning the status of command */
2527 };
2528
2529 /**
2530 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
2531 */
2532 struct dmub_rb_cmd_query_hpd_state {
2533 /**
2534 * Command header.
2535 */
2536 struct dmub_cmd_header header;
2537 /**
2538 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
2539 */
2540 struct dmub_cmd_hpd_state_query_data data;
2541 };
2542
2543 /**
2544 * struct dmub_rb_cmd_hpd_sense_notify - HPD sense notification data.
2545 */
2546 struct dmub_rb_cmd_hpd_sense_notify_data {
2547 uint32_t old_hpd_sense_mask; /**< Old HPD sense mask */
2548 uint32_t new_hpd_sense_mask; /**< New HPD sense mask */
2549 };
2550
2551 /**
2552 * struct dmub_rb_cmd_hpd_sense_notify - DMUB_OUT_CMD__HPD_SENSE_NOTIFY command.
2553 */
2554 struct dmub_rb_cmd_hpd_sense_notify {
2555 struct dmub_cmd_header header; /**< header */
2556 struct dmub_rb_cmd_hpd_sense_notify_data data; /**< payload */
2557 };
2558
2559 /*
2560 * Command IDs should be treated as stable ABI.
2561 * Do not reuse or modify IDs.
2562 */
2563
2564 /**
2565 * PSR command sub-types.
2566 */
2567 enum dmub_cmd_psr_type {
2568 /**
2569 * Set PSR version support.
2570 */
2571 DMUB_CMD__PSR_SET_VERSION = 0,
2572 /**
2573 * Copy driver-calculated parameters to PSR state.
2574 */
2575 DMUB_CMD__PSR_COPY_SETTINGS = 1,
2576 /**
2577 * Enable PSR.
2578 */
2579 DMUB_CMD__PSR_ENABLE = 2,
2580
2581 /**
2582 * Disable PSR.
2583 */
2584 DMUB_CMD__PSR_DISABLE = 3,
2585
2586 /**
2587 * Set PSR level.
2588 * PSR level is a 16-bit value dicated by driver that
2589 * will enable/disable different functionality.
2590 */
2591 DMUB_CMD__PSR_SET_LEVEL = 4,
2592
2593 /**
2594 * Forces PSR enabled until an explicit PSR disable call.
2595 */
2596 DMUB_CMD__PSR_FORCE_STATIC = 5,
2597 /**
2598 * Set vtotal in psr active for FreeSync PSR.
2599 */
2600 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
2601 /**
2602 * Set PSR power option
2603 */
2604 DMUB_CMD__SET_PSR_POWER_OPT = 7,
2605 };
2606
2607 /**
2608 * Different PSR residency modes.
2609 * Different modes change the definition of PSR residency.
2610 */
2611 enum psr_residency_mode {
2612 PSR_RESIDENCY_MODE_PHY = 0,
2613 PSR_RESIDENCY_MODE_ALPM,
2614 PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
2615 /* Do not add below. */
2616 PSR_RESIDENCY_MODE_LAST_ELEMENT,
2617 };
2618
2619 enum dmub_cmd_fams_type {
2620 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
2621 DMUB_CMD__FAMS_DRR_UPDATE = 1,
2622 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
2623 /**
2624 * For SubVP set manual trigger in FW because it
2625 * triggers DRR_UPDATE_PENDING which SubVP relies
2626 * on (for any SubVP cases that use a DRR display)
2627 */
2628 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
2629 DMUB_CMD__FAMS2_CONFIG = 4,
2630 DMUB_CMD__FAMS2_DRR_UPDATE = 5,
2631 DMUB_CMD__FAMS2_FLIP = 6,
2632 };
2633
2634 /**
2635 * PSR versions.
2636 */
2637 enum psr_version {
2638 /**
2639 * PSR version 1.
2640 */
2641 PSR_VERSION_1 = 0,
2642 /**
2643 * Freesync PSR SU.
2644 */
2645 PSR_VERSION_SU_1 = 1,
2646 /**
2647 * PSR not supported.
2648 */
2649 PSR_VERSION_UNSUPPORTED = 0xFF, // psr_version field is only 8 bits wide
2650 };
2651
2652 /**
2653 * PHY Link rate for DP.
2654 */
2655 enum phy_link_rate {
2656 /**
2657 * not supported.
2658 */
2659 PHY_RATE_UNKNOWN = 0,
2660 /**
2661 * Rate_1 (RBR) - 1.62 Gbps/Lane
2662 */
2663 PHY_RATE_162 = 1,
2664 /**
2665 * Rate_2 - 2.16 Gbps/Lane
2666 */
2667 PHY_RATE_216 = 2,
2668 /**
2669 * Rate_3 - 2.43 Gbps/Lane
2670 */
2671 PHY_RATE_243 = 3,
2672 /**
2673 * Rate_4 (HBR) - 2.70 Gbps/Lane
2674 */
2675 PHY_RATE_270 = 4,
2676 /**
2677 * Rate_5 (RBR2)- 3.24 Gbps/Lane
2678 */
2679 PHY_RATE_324 = 5,
2680 /**
2681 * Rate_6 - 4.32 Gbps/Lane
2682 */
2683 PHY_RATE_432 = 6,
2684 /**
2685 * Rate_7 (HBR2)- 5.40 Gbps/Lane
2686 */
2687 PHY_RATE_540 = 7,
2688 /**
2689 * Rate_8 (HBR3)- 8.10 Gbps/Lane
2690 */
2691 PHY_RATE_810 = 8,
2692 /**
2693 * UHBR10 - 10.0 Gbps/Lane
2694 */
2695 PHY_RATE_1000 = 9,
2696 /**
2697 * UHBR13.5 - 13.5 Gbps/Lane
2698 */
2699 PHY_RATE_1350 = 10,
2700 /**
2701 * UHBR10 - 20.0 Gbps/Lane
2702 */
2703 PHY_RATE_2000 = 11,
2704
2705 PHY_RATE_675 = 12,
2706 /**
2707 * Rate 12 - 6.75 Gbps/Lane
2708 */
2709 };
2710
2711 /**
2712 * enum dmub_phy_fsm_state - PHY FSM states.
2713 * PHY FSM state to transit to during PSR enable/disable.
2714 */
2715 enum dmub_phy_fsm_state {
2716 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
2717 DMUB_PHY_FSM_RESET,
2718 DMUB_PHY_FSM_RESET_RELEASED,
2719 DMUB_PHY_FSM_SRAM_LOAD_DONE,
2720 DMUB_PHY_FSM_INITIALIZED,
2721 DMUB_PHY_FSM_CALIBRATED,
2722 DMUB_PHY_FSM_CALIBRATED_LP,
2723 DMUB_PHY_FSM_CALIBRATED_PG,
2724 DMUB_PHY_FSM_POWER_DOWN,
2725 DMUB_PHY_FSM_PLL_EN,
2726 DMUB_PHY_FSM_TX_EN,
2727 DMUB_PHY_FSM_TX_EN_TEST_MODE,
2728 DMUB_PHY_FSM_FAST_LP,
2729 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
2730 DMUB_PHY_FSM_P2_PLL_OFF_PG,
2731 DMUB_PHY_FSM_P2_PLL_OFF,
2732 DMUB_PHY_FSM_P2_PLL_ON,
2733 };
2734
2735 /**
2736 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2737 */
2738 struct dmub_cmd_psr_copy_settings_data {
2739 /**
2740 * Flags that can be set by driver to change some PSR behaviour.
2741 */
2742 union dmub_psr_debug_flags debug;
2743 /**
2744 * 16-bit value dicated by driver that will enable/disable different functionality.
2745 */
2746 uint16_t psr_level;
2747 /**
2748 * DPP HW instance.
2749 */
2750 uint8_t dpp_inst;
2751 /**
2752 * MPCC HW instance.
2753 * Not used in dmub fw,
2754 * dmub fw will get active opp by reading odm registers.
2755 */
2756 uint8_t mpcc_inst;
2757 /**
2758 * OPP HW instance.
2759 * Not used in dmub fw,
2760 * dmub fw will get active opp by reading odm registers.
2761 */
2762 uint8_t opp_inst;
2763 /**
2764 * OTG HW instance.
2765 */
2766 uint8_t otg_inst;
2767 /**
2768 * DIG FE HW instance.
2769 */
2770 uint8_t digfe_inst;
2771 /**
2772 * DIG BE HW instance.
2773 */
2774 uint8_t digbe_inst;
2775 /**
2776 * DP PHY HW instance.
2777 */
2778 uint8_t dpphy_inst;
2779 /**
2780 * AUX HW instance.
2781 */
2782 uint8_t aux_inst;
2783 /**
2784 * Determines if SMU optimzations are enabled/disabled.
2785 */
2786 uint8_t smu_optimizations_en;
2787 /**
2788 * Unused.
2789 * TODO: Remove.
2790 */
2791 uint8_t frame_delay;
2792 /**
2793 * If RFB setup time is greater than the total VBLANK time,
2794 * it is not possible for the sink to capture the video frame
2795 * in the same frame the SDP is sent. In this case,
2796 * the frame capture indication bit should be set and an extra
2797 * static frame should be transmitted to the sink.
2798 */
2799 uint8_t frame_cap_ind;
2800 /**
2801 * Granularity of Y offset supported by sink.
2802 */
2803 uint8_t su_y_granularity;
2804 /**
2805 * Indicates whether sink should start capturing
2806 * immediately following active scan line,
2807 * or starting with the 2nd active scan line.
2808 */
2809 uint8_t line_capture_indication;
2810 /**
2811 * Multi-display optimizations are implemented on certain ASICs.
2812 */
2813 uint8_t multi_disp_optimizations_en;
2814 /**
2815 * The last possible line SDP may be transmitted without violating
2816 * the RFB setup time or entering the active video frame.
2817 */
2818 uint16_t init_sdp_deadline;
2819 /**
2820 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
2821 */
2822 uint8_t rate_control_caps ;
2823 /*
2824 * Force PSRSU always doing full frame update
2825 */
2826 uint8_t force_ffu_mode;
2827 /**
2828 * Length of each horizontal line in us.
2829 */
2830 uint32_t line_time_in_us;
2831 /**
2832 * FEC enable status in driver
2833 */
2834 uint8_t fec_enable_status;
2835 /**
2836 * FEC re-enable delay when PSR exit.
2837 * unit is 100us, range form 0~255(0xFF).
2838 */
2839 uint8_t fec_enable_delay_in100us;
2840 /**
2841 * PSR control version.
2842 */
2843 uint8_t cmd_version;
2844 /**
2845 * Panel Instance.
2846 * Panel instance to identify which psr_state to use
2847 * Currently the support is only for 0 or 1
2848 */
2849 uint8_t panel_inst;
2850 /*
2851 * DSC enable status in driver
2852 */
2853 uint8_t dsc_enable_status;
2854 /*
2855 * Use FSM state for PSR power up/down
2856 */
2857 uint8_t use_phy_fsm;
2858 /**
2859 * frame delay for frame re-lock
2860 */
2861 uint8_t relock_delay_frame_cnt;
2862 /**
2863 * esd recovery indicate.
2864 */
2865 uint8_t esd_recovery;
2866 /**
2867 * DSC Slice height.
2868 */
2869 uint16_t dsc_slice_height;
2870 /**
2871 * Some panels request main link off before xth vertical line
2872 */
2873 uint16_t poweroff_before_vertical_line;
2874 };
2875
2876 /**
2877 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2878 */
2879 struct dmub_rb_cmd_psr_copy_settings {
2880 /**
2881 * Command header.
2882 */
2883 struct dmub_cmd_header header;
2884 /**
2885 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2886 */
2887 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
2888 };
2889
2890 /**
2891 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
2892 */
2893 struct dmub_cmd_psr_set_level_data {
2894 /**
2895 * 16-bit value dicated by driver that will enable/disable different functionality.
2896 */
2897 uint16_t psr_level;
2898 /**
2899 * PSR control version.
2900 */
2901 uint8_t cmd_version;
2902 /**
2903 * Panel Instance.
2904 * Panel instance to identify which psr_state to use
2905 * Currently the support is only for 0 or 1
2906 */
2907 uint8_t panel_inst;
2908 };
2909
2910 /**
2911 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2912 */
2913 struct dmub_rb_cmd_psr_set_level {
2914 /**
2915 * Command header.
2916 */
2917 struct dmub_cmd_header header;
2918 /**
2919 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2920 */
2921 struct dmub_cmd_psr_set_level_data psr_set_level_data;
2922 };
2923
2924 struct dmub_rb_cmd_psr_enable_data {
2925 /**
2926 * PSR control version.
2927 */
2928 uint8_t cmd_version;
2929 /**
2930 * Panel Instance.
2931 * Panel instance to identify which psr_state to use
2932 * Currently the support is only for 0 or 1
2933 */
2934 uint8_t panel_inst;
2935 /**
2936 * Phy state to enter.
2937 * Values to use are defined in dmub_phy_fsm_state
2938 */
2939 uint8_t phy_fsm_state;
2940 /**
2941 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2942 * Set this using enum phy_link_rate.
2943 * This does not support HDMI/DP2 for now.
2944 */
2945 uint8_t phy_rate;
2946 };
2947
2948 /**
2949 * Definition of a DMUB_CMD__PSR_ENABLE command.
2950 * PSR enable/disable is controlled using the sub_type.
2951 */
2952 struct dmub_rb_cmd_psr_enable {
2953 /**
2954 * Command header.
2955 */
2956 struct dmub_cmd_header header;
2957
2958 struct dmub_rb_cmd_psr_enable_data data;
2959 };
2960
2961 /**
2962 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2963 */
2964 struct dmub_cmd_psr_set_version_data {
2965 /**
2966 * PSR version that FW should implement.
2967 */
2968 enum psr_version version;
2969 /**
2970 * PSR control version.
2971 */
2972 uint8_t cmd_version;
2973 /**
2974 * Panel Instance.
2975 * Panel instance to identify which psr_state to use
2976 * Currently the support is only for 0 or 1
2977 */
2978 uint8_t panel_inst;
2979 /**
2980 * Explicit padding to 4 byte boundary.
2981 */
2982 uint8_t pad[2];
2983 };
2984
2985 /**
2986 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2987 */
2988 struct dmub_rb_cmd_psr_set_version {
2989 /**
2990 * Command header.
2991 */
2992 struct dmub_cmd_header header;
2993 /**
2994 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2995 */
2996 struct dmub_cmd_psr_set_version_data psr_set_version_data;
2997 };
2998
2999 struct dmub_cmd_psr_force_static_data {
3000 /**
3001 * PSR control version.
3002 */
3003 uint8_t cmd_version;
3004 /**
3005 * Panel Instance.
3006 * Panel instance to identify which psr_state to use
3007 * Currently the support is only for 0 or 1
3008 */
3009 uint8_t panel_inst;
3010 /**
3011 * Explicit padding to 4 byte boundary.
3012 */
3013 uint8_t pad[2];
3014 };
3015
3016 /**
3017 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3018 */
3019 struct dmub_rb_cmd_psr_force_static {
3020 /**
3021 * Command header.
3022 */
3023 struct dmub_cmd_header header;
3024 /**
3025 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
3026 */
3027 struct dmub_cmd_psr_force_static_data psr_force_static_data;
3028 };
3029
3030 /**
3031 * PSR SU debug flags.
3032 */
3033 union dmub_psr_su_debug_flags {
3034 /**
3035 * PSR SU debug flags.
3036 */
3037 struct {
3038 /**
3039 * Update dirty rect in SW only.
3040 */
3041 uint8_t update_dirty_rect_only : 1;
3042 /**
3043 * Reset the cursor/plane state before processing the call.
3044 */
3045 uint8_t reset_state : 1;
3046 } bitfields;
3047
3048 /**
3049 * Union for debug flags.
3050 */
3051 uint32_t u32All;
3052 };
3053
3054 /**
3055 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3056 * This triggers a selective update for PSR SU.
3057 */
3058 struct dmub_cmd_update_dirty_rect_data {
3059 /**
3060 * Dirty rects from OS.
3061 */
3062 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
3063 /**
3064 * PSR SU debug flags.
3065 */
3066 union dmub_psr_su_debug_flags debug_flags;
3067 /**
3068 * OTG HW instance.
3069 */
3070 uint8_t pipe_idx;
3071 /**
3072 * Number of dirty rects.
3073 */
3074 uint8_t dirty_rect_count;
3075 /**
3076 * PSR control version.
3077 */
3078 uint8_t cmd_version;
3079 /**
3080 * Panel Instance.
3081 * Panel instance to identify which psr_state to use
3082 * Currently the support is only for 0 or 1
3083 */
3084 uint8_t panel_inst;
3085 };
3086
3087 /**
3088 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3089 */
3090 struct dmub_rb_cmd_update_dirty_rect {
3091 /**
3092 * Command header.
3093 */
3094 struct dmub_cmd_header header;
3095 /**
3096 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
3097 */
3098 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
3099 };
3100
3101 /**
3102 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
3103 */
3104 union dmub_reg_cursor_control_cfg {
3105 struct {
3106 uint32_t cur_enable: 1;
3107 uint32_t reser0: 3;
3108 uint32_t cur_2x_magnify: 1;
3109 uint32_t reser1: 3;
3110 uint32_t mode: 3;
3111 uint32_t reser2: 5;
3112 uint32_t pitch: 2;
3113 uint32_t reser3: 6;
3114 uint32_t line_per_chunk: 5;
3115 uint32_t reser4: 3;
3116 } bits;
3117 uint32_t raw;
3118 };
3119 struct dmub_cursor_position_cache_hubp {
3120 union dmub_reg_cursor_control_cfg cur_ctl;
3121 union dmub_reg_position_cfg {
3122 struct {
3123 uint32_t cur_x_pos: 16;
3124 uint32_t cur_y_pos: 16;
3125 } bits;
3126 uint32_t raw;
3127 } position;
3128 union dmub_reg_hot_spot_cfg {
3129 struct {
3130 uint32_t hot_x: 16;
3131 uint32_t hot_y: 16;
3132 } bits;
3133 uint32_t raw;
3134 } hot_spot;
3135 union dmub_reg_dst_offset_cfg {
3136 struct {
3137 uint32_t dst_x_offset: 13;
3138 uint32_t reserved: 19;
3139 } bits;
3140 uint32_t raw;
3141 } dst_offset;
3142 };
3143
3144 union dmub_reg_cur0_control_cfg {
3145 struct {
3146 uint32_t cur0_enable: 1;
3147 uint32_t expansion_mode: 1;
3148 uint32_t reser0: 1;
3149 uint32_t cur0_rom_en: 1;
3150 uint32_t mode: 3;
3151 uint32_t reserved: 25;
3152 } bits;
3153 uint32_t raw;
3154 };
3155 struct dmub_cursor_position_cache_dpp {
3156 union dmub_reg_cur0_control_cfg cur0_ctl;
3157 };
3158 struct dmub_cursor_position_cfg {
3159 struct dmub_cursor_position_cache_hubp pHubp;
3160 struct dmub_cursor_position_cache_dpp pDpp;
3161 uint8_t pipe_idx;
3162 /*
3163 * Padding is required. To be 4 Bytes Aligned.
3164 */
3165 uint8_t padding[3];
3166 };
3167
3168 struct dmub_cursor_attribute_cache_hubp {
3169 uint32_t SURFACE_ADDR_HIGH;
3170 uint32_t SURFACE_ADDR;
3171 union dmub_reg_cursor_control_cfg cur_ctl;
3172 union dmub_reg_cursor_size_cfg {
3173 struct {
3174 uint32_t width: 16;
3175 uint32_t height: 16;
3176 } bits;
3177 uint32_t raw;
3178 } size;
3179 union dmub_reg_cursor_settings_cfg {
3180 struct {
3181 uint32_t dst_y_offset: 8;
3182 uint32_t chunk_hdl_adjust: 2;
3183 uint32_t reserved: 22;
3184 } bits;
3185 uint32_t raw;
3186 } settings;
3187 };
3188 struct dmub_cursor_attribute_cache_dpp {
3189 union dmub_reg_cur0_control_cfg cur0_ctl;
3190 };
3191 struct dmub_cursor_attributes_cfg {
3192 struct dmub_cursor_attribute_cache_hubp aHubp;
3193 struct dmub_cursor_attribute_cache_dpp aDpp;
3194 };
3195
3196 struct dmub_cmd_update_cursor_payload0 {
3197 /**
3198 * Cursor dirty rects.
3199 */
3200 struct dmub_rect cursor_rect;
3201 /**
3202 * PSR SU debug flags.
3203 */
3204 union dmub_psr_su_debug_flags debug_flags;
3205 /**
3206 * Cursor enable/disable.
3207 */
3208 uint8_t enable;
3209 /**
3210 * OTG HW instance.
3211 */
3212 uint8_t pipe_idx;
3213 /**
3214 * PSR control version.
3215 */
3216 uint8_t cmd_version;
3217 /**
3218 * Panel Instance.
3219 * Panel instance to identify which psr_state to use
3220 * Currently the support is only for 0 or 1
3221 */
3222 uint8_t panel_inst;
3223 /**
3224 * Cursor Position Register.
3225 * Registers contains Hubp & Dpp modules
3226 */
3227 struct dmub_cursor_position_cfg position_cfg;
3228 };
3229
3230 struct dmub_cmd_update_cursor_payload1 {
3231 struct dmub_cursor_attributes_cfg attribute_cfg;
3232 };
3233
3234 union dmub_cmd_update_cursor_info_data {
3235 struct dmub_cmd_update_cursor_payload0 payload0;
3236 struct dmub_cmd_update_cursor_payload1 payload1;
3237 };
3238 /**
3239 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3240 */
3241 struct dmub_rb_cmd_update_cursor_info {
3242 /**
3243 * Command header.
3244 */
3245 struct dmub_cmd_header header;
3246 /**
3247 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
3248 */
3249 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
3250 };
3251
3252 /**
3253 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3254 */
3255 struct dmub_cmd_psr_set_vtotal_data {
3256 /**
3257 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
3258 */
3259 uint16_t psr_vtotal_idle;
3260 /**
3261 * PSR control version.
3262 */
3263 uint8_t cmd_version;
3264 /**
3265 * Panel Instance.
3266 * Panel instance to identify which psr_state to use
3267 * Currently the support is only for 0 or 1
3268 */
3269 uint8_t panel_inst;
3270 /*
3271 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
3272 */
3273 uint16_t psr_vtotal_su;
3274 /**
3275 * Explicit padding to 4 byte boundary.
3276 */
3277 uint8_t pad2[2];
3278 };
3279
3280 /**
3281 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3282 */
3283 struct dmub_rb_cmd_psr_set_vtotal {
3284 /**
3285 * Command header.
3286 */
3287 struct dmub_cmd_header header;
3288 /**
3289 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3290 */
3291 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
3292 };
3293
3294 /**
3295 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
3296 */
3297 struct dmub_cmd_psr_set_power_opt_data {
3298 /**
3299 * PSR control version.
3300 */
3301 uint8_t cmd_version;
3302 /**
3303 * Panel Instance.
3304 * Panel instance to identify which psr_state to use
3305 * Currently the support is only for 0 or 1
3306 */
3307 uint8_t panel_inst;
3308 /**
3309 * Explicit padding to 4 byte boundary.
3310 */
3311 uint8_t pad[2];
3312 /**
3313 * PSR power option
3314 */
3315 uint32_t power_opt;
3316 };
3317
3318 /**
3319 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3320 */
3321 struct dmub_rb_cmd_psr_set_power_opt {
3322 /**
3323 * Command header.
3324 */
3325 struct dmub_cmd_header header;
3326 /**
3327 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3328 */
3329 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
3330 };
3331
3332 /**
3333 * Definition of Replay Residency GPINT command.
3334 * Bit[0] - Residency mode for Revision 0
3335 * Bit[1] - Enable/Disable state
3336 * Bit[2-3] - Revision number
3337 * Bit[4-7] - Residency mode for Revision 1
3338 * Bit[8] - Panel instance
3339 * Bit[9-15] - Reserved
3340 */
3341
3342 enum pr_residency_mode {
3343 PR_RESIDENCY_MODE_PHY = 0x0,
3344 PR_RESIDENCY_MODE_ALPM,
3345 PR_RESIDENCY_MODE_IPS2,
3346 PR_RESIDENCY_MODE_FRAME_CNT,
3347 PR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
3348 };
3349
3350 #define REPLAY_RESIDENCY_MODE_SHIFT (0)
3351 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
3352 #define REPLAY_RESIDENCY_REVISION_SHIFT (2)
3353 #define REPLAY_RESIDENCY_MODE2_SHIFT (4)
3354
3355 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
3356 # define REPLAY_RESIDENCY_FIELD_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
3357 # define REPLAY_RESIDENCY_FIELD_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
3358
3359 #define REPLAY_RESIDENCY_MODE2_MASK (0xF << REPLAY_RESIDENCY_MODE2_SHIFT)
3360 # define REPLAY_RESIDENCY_FIELD_MODE2_IPS (0x1 << REPLAY_RESIDENCY_MODE2_SHIFT)
3361 # define REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT (0x2 << REPLAY_RESIDENCY_MODE2_SHIFT)
3362 # define REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD (0x3 << REPLAY_RESIDENCY_MODE2_SHIFT)
3363
3364 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3365 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3366 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
3367
3368 #define REPLAY_RESIDENCY_REVISION_MASK (0x3 << REPLAY_RESIDENCY_REVISION_SHIFT)
3369 # define REPLAY_RESIDENCY_REVISION_0 (0x0 << REPLAY_RESIDENCY_REVISION_SHIFT)
3370 # define REPLAY_RESIDENCY_REVISION_1 (0x1 << REPLAY_RESIDENCY_REVISION_SHIFT)
3371
3372 /**
3373 * Definition of a replay_state.
3374 */
3375 enum replay_state {
3376 REPLAY_STATE_0 = 0x0,
3377 REPLAY_STATE_1 = 0x10,
3378 REPLAY_STATE_1A = 0x11,
3379 REPLAY_STATE_2 = 0x20,
3380 REPLAY_STATE_2A = 0x21,
3381 REPLAY_STATE_3 = 0x30,
3382 REPLAY_STATE_3INIT = 0x31,
3383 REPLAY_STATE_4 = 0x40,
3384 REPLAY_STATE_4A = 0x41,
3385 REPLAY_STATE_4B = 0x42,
3386 REPLAY_STATE_4C = 0x43,
3387 REPLAY_STATE_4D = 0x44,
3388 REPLAY_STATE_4E = 0x45,
3389 REPLAY_STATE_4B_LOCKED = 0x4A,
3390 REPLAY_STATE_4C_UNLOCKED = 0x4B,
3391 REPLAY_STATE_5 = 0x50,
3392 REPLAY_STATE_5A = 0x51,
3393 REPLAY_STATE_5B = 0x52,
3394 REPLAY_STATE_5A_LOCKED = 0x5A,
3395 REPLAY_STATE_5B_UNLOCKED = 0x5B,
3396 REPLAY_STATE_6 = 0x60,
3397 REPLAY_STATE_6A = 0x61,
3398 REPLAY_STATE_6B = 0x62,
3399 REPLAY_STATE_INVALID = 0xFF,
3400 };
3401
3402 /**
3403 * Replay command sub-types.
3404 */
3405 enum dmub_cmd_replay_type {
3406 /**
3407 * Copy driver-calculated parameters to REPLAY state.
3408 */
3409 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
3410 /**
3411 * Enable REPLAY.
3412 */
3413 DMUB_CMD__REPLAY_ENABLE = 1,
3414 /**
3415 * Set Replay power option.
3416 */
3417 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
3418 /**
3419 * Set coasting vtotal.
3420 */
3421 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
3422 /**
3423 * Set power opt and coasting vtotal.
3424 */
3425 DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL = 4,
3426 /**
3427 * Set disabled iiming sync.
3428 */
3429 DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED = 5,
3430 /**
3431 * Set Residency Frameupdate Timer.
3432 */
3433 DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER = 6,
3434 /**
3435 * Set pseudo vtotal
3436 */
3437 DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL = 7,
3438 /**
3439 * Set adaptive sync sdp enabled
3440 */
3441 DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
3442 /**
3443 * Set Replay General command.
3444 */
3445 DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,
3446 };
3447
3448 /**
3449 * Replay general command sub-types.
3450 */
3451 enum dmub_cmd_replay_general_subtype {
3452 REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,
3453 /**
3454 * TODO: For backward compatible, allow new command only.
3455 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,
3456 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,
3457 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,
3458 */
3459 REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,
3460 REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
3461 };
3462
3463 /**
3464 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3465 */
3466 struct dmub_cmd_replay_copy_settings_data {
3467 /**
3468 * Flags that can be set by driver to change some replay behaviour.
3469 */
3470 union replay_debug_flags debug;
3471
3472 /**
3473 * @flags: Flags used to determine feature functionality.
3474 */
3475 union replay_hw_flags flags;
3476
3477 /**
3478 * DPP HW instance.
3479 */
3480 uint8_t dpp_inst;
3481 /**
3482 * OTG HW instance.
3483 */
3484 uint8_t otg_inst;
3485 /**
3486 * DIG FE HW instance.
3487 */
3488 uint8_t digfe_inst;
3489 /**
3490 * DIG BE HW instance.
3491 */
3492 uint8_t digbe_inst;
3493 /**
3494 * AUX HW instance.
3495 */
3496 uint8_t aux_inst;
3497 /**
3498 * Panel Instance.
3499 * Panel isntance to identify which psr_state to use
3500 * Currently the support is only for 0 or 1
3501 */
3502 uint8_t panel_inst;
3503 /**
3504 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
3505 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
3506 */
3507 uint8_t pixel_deviation_per_line;
3508 /**
3509 * @max_deviation_line: The max number of deviation line that can keep the timing
3510 * synchronized between the Source and Sink during Replay normal sleep mode.
3511 */
3512 uint8_t max_deviation_line;
3513 /**
3514 * Length of each horizontal line in ns.
3515 */
3516 uint32_t line_time_in_ns;
3517 /**
3518 * PHY instance.
3519 */
3520 uint8_t dpphy_inst;
3521 /**
3522 * Determines if SMU optimzations are enabled/disabled.
3523 */
3524 uint8_t smu_optimizations_en;
3525 /**
3526 * Determines if timing sync are enabled/disabled.
3527 */
3528 uint8_t replay_timing_sync_supported;
3529 /*
3530 * Use FSM state for Replay power up/down
3531 */
3532 uint8_t use_phy_fsm;
3533 };
3534
3535 /**
3536 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3537 */
3538 struct dmub_rb_cmd_replay_copy_settings {
3539 /**
3540 * Command header.
3541 */
3542 struct dmub_cmd_header header;
3543 /**
3544 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
3545 */
3546 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
3547 };
3548
3549 /**
3550 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
3551 */
3552 enum replay_enable {
3553 /**
3554 * Disable REPLAY.
3555 */
3556 REPLAY_DISABLE = 0,
3557 /**
3558 * Enable REPLAY.
3559 */
3560 REPLAY_ENABLE = 1,
3561 };
3562
3563 /**
3564 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
3565 */
3566 struct dmub_rb_cmd_replay_enable_data {
3567 /**
3568 * Replay enable or disable.
3569 */
3570 uint8_t enable;
3571 /**
3572 * Panel Instance.
3573 * Panel isntance to identify which replay_state to use
3574 * Currently the support is only for 0 or 1
3575 */
3576 uint8_t panel_inst;
3577 /**
3578 * Phy state to enter.
3579 * Values to use are defined in dmub_phy_fsm_state
3580 */
3581 uint8_t phy_fsm_state;
3582 /**
3583 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
3584 * Set this using enum phy_link_rate.
3585 * This does not support HDMI/DP2 for now.
3586 */
3587 uint8_t phy_rate;
3588 };
3589
3590 /**
3591 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
3592 * Replay enable/disable is controlled using action in data.
3593 */
3594 struct dmub_rb_cmd_replay_enable {
3595 /**
3596 * Command header.
3597 */
3598 struct dmub_cmd_header header;
3599
3600 struct dmub_rb_cmd_replay_enable_data data;
3601 };
3602
3603 /**
3604 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3605 */
3606 struct dmub_cmd_replay_set_power_opt_data {
3607 /**
3608 * Panel Instance.
3609 * Panel isntance to identify which replay_state to use
3610 * Currently the support is only for 0 or 1
3611 */
3612 uint8_t panel_inst;
3613 /**
3614 * Explicit padding to 4 byte boundary.
3615 */
3616 uint8_t pad[3];
3617 /**
3618 * REPLAY power option
3619 */
3620 uint32_t power_opt;
3621 };
3622
3623 /**
3624 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3625 */
3626 struct dmub_cmd_replay_set_timing_sync_data {
3627 /**
3628 * Panel Instance.
3629 * Panel isntance to identify which replay_state to use
3630 * Currently the support is only for 0 or 1
3631 */
3632 uint8_t panel_inst;
3633 /**
3634 * REPLAY set_timing_sync
3635 */
3636 uint8_t timing_sync_supported;
3637 /**
3638 * Explicit padding to 4 byte boundary.
3639 */
3640 uint8_t pad[2];
3641 };
3642
3643 /**
3644 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3645 */
3646 struct dmub_cmd_replay_set_pseudo_vtotal {
3647 /**
3648 * Panel Instance.
3649 * Panel isntance to identify which replay_state to use
3650 * Currently the support is only for 0 or 1
3651 */
3652 uint8_t panel_inst;
3653 /**
3654 * Source Vtotal that Replay + IPS + ABM full screen video src vtotal
3655 */
3656 uint16_t vtotal;
3657 /**
3658 * Explicit padding to 4 byte boundary.
3659 */
3660 uint8_t pad;
3661 };
3662 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
3663 /**
3664 * Panel Instance.
3665 * Panel isntance to identify which replay_state to use
3666 * Currently the support is only for 0 or 1
3667 */
3668 uint8_t panel_inst;
3669 /**
3670 * enabled: set adaptive sync sdp enabled
3671 */
3672 uint8_t force_disabled;
3673
3674 uint8_t pad[2];
3675 };
3676 struct dmub_cmd_replay_set_general_cmd_data {
3677 /**
3678 * Panel Instance.
3679 * Panel isntance to identify which replay_state to use
3680 * Currently the support is only for 0 or 1
3681 */
3682 uint8_t panel_inst;
3683 /**
3684 * subtype: replay general cmd sub type
3685 */
3686 uint8_t subtype;
3687
3688 uint8_t pad[2];
3689 /**
3690 * config data with param1 and param2
3691 */
3692 uint32_t param1;
3693
3694 uint32_t param2;
3695 };
3696
3697 /**
3698 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3699 */
3700 struct dmub_rb_cmd_replay_set_power_opt {
3701 /**
3702 * Command header.
3703 */
3704 struct dmub_cmd_header header;
3705 /**
3706 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3707 */
3708 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
3709 };
3710
3711 /**
3712 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3713 */
3714 struct dmub_cmd_replay_set_coasting_vtotal_data {
3715 /**
3716 * 16-bit value dicated by driver that indicates the coasting vtotal.
3717 */
3718 uint16_t coasting_vtotal;
3719 /**
3720 * REPLAY control version.
3721 */
3722 uint8_t cmd_version;
3723 /**
3724 * Panel Instance.
3725 * Panel isntance to identify which replay_state to use
3726 * Currently the support is only for 0 or 1
3727 */
3728 uint8_t panel_inst;
3729 /**
3730 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.
3731 */
3732 uint16_t coasting_vtotal_high;
3733 /**
3734 * Explicit padding to 4 byte boundary.
3735 */
3736 uint8_t pad[2];
3737 };
3738
3739 /**
3740 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3741 */
3742 struct dmub_rb_cmd_replay_set_coasting_vtotal {
3743 /**
3744 * Command header.
3745 */
3746 struct dmub_cmd_header header;
3747 /**
3748 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3749 */
3750 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3751 };
3752
3753 /**
3754 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
3755 */
3756 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal {
3757 /**
3758 * Command header.
3759 */
3760 struct dmub_cmd_header header;
3761 /**
3762 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3763 */
3764 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
3765 /**
3766 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
3767 */
3768 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3769 };
3770
3771 /**
3772 * Definition of a DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3773 */
3774 struct dmub_rb_cmd_replay_set_timing_sync {
3775 /**
3776 * Command header.
3777 */
3778 struct dmub_cmd_header header;
3779 /**
3780 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command.
3781 */
3782 struct dmub_cmd_replay_set_timing_sync_data replay_set_timing_sync_data;
3783 };
3784
3785 /**
3786 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3787 */
3788 struct dmub_rb_cmd_replay_set_pseudo_vtotal {
3789 /**
3790 * Command header.
3791 */
3792 struct dmub_cmd_header header;
3793 /**
3794 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
3795 */
3796 struct dmub_cmd_replay_set_pseudo_vtotal data;
3797 };
3798
3799 /**
3800 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
3801 */
3802 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
3803 /**
3804 * Command header.
3805 */
3806 struct dmub_cmd_header header;
3807 /**
3808 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
3809 */
3810 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
3811 };
3812
3813 /**
3814 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
3815 */
3816 struct dmub_rb_cmd_replay_set_general_cmd {
3817 /**
3818 * Command header.
3819 */
3820 struct dmub_cmd_header header;
3821 /**
3822 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
3823 */
3824 struct dmub_cmd_replay_set_general_cmd_data data;
3825 };
3826
3827 /**
3828 * Data passed from driver to FW in DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
3829 */
3830 struct dmub_cmd_replay_frameupdate_timer_data {
3831 /**
3832 * Panel Instance.
3833 * Panel isntance to identify which replay_state to use
3834 * Currently the support is only for 0 or 1
3835 */
3836 uint8_t panel_inst;
3837 /**
3838 * Replay Frameupdate Timer Enable or not
3839 */
3840 uint8_t enable;
3841 /**
3842 * REPLAY force reflash frame update number
3843 */
3844 uint16_t frameupdate_count;
3845 };
3846 /**
3847 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER
3848 */
3849 struct dmub_rb_cmd_replay_set_frameupdate_timer {
3850 /**
3851 * Command header.
3852 */
3853 struct dmub_cmd_header header;
3854 /**
3855 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
3856 */
3857 struct dmub_cmd_replay_frameupdate_timer_data data;
3858 };
3859
3860 /**
3861 * Definition union of replay command set
3862 */
3863 union dmub_replay_cmd_set {
3864 /**
3865 * Panel Instance.
3866 * Panel isntance to identify which replay_state to use
3867 * Currently the support is only for 0 or 1
3868 */
3869 uint8_t panel_inst;
3870 /**
3871 * Definition of DMUB_CMD__REPLAY_SET_TIMING_SYNC_SUPPORTED command data.
3872 */
3873 struct dmub_cmd_replay_set_timing_sync_data sync_data;
3874 /**
3875 * Definition of DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command data.
3876 */
3877 struct dmub_cmd_replay_frameupdate_timer_data timer_data;
3878 /**
3879 * Definition of DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command data.
3880 */
3881 struct dmub_cmd_replay_set_pseudo_vtotal pseudo_vtotal_data;
3882 /**
3883 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.
3884 */
3885 struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;
3886 /**
3887 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.
3888 */
3889 struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;
3890 };
3891
3892 /**
3893 * Set of HW components that can be locked.
3894 *
3895 * Note: If updating with more HW components, fields
3896 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3897 */
3898 union dmub_hw_lock_flags {
3899 /**
3900 * Set of HW components that can be locked.
3901 */
3902 struct {
3903 /**
3904 * Lock/unlock OTG master update lock.
3905 */
3906 uint8_t lock_pipe : 1;
3907 /**
3908 * Lock/unlock cursor.
3909 */
3910 uint8_t lock_cursor : 1;
3911 /**
3912 * Lock/unlock global update lock.
3913 */
3914 uint8_t lock_dig : 1;
3915 /**
3916 * Triple buffer lock requires additional hw programming to usual OTG master lock.
3917 */
3918 uint8_t triple_buffer_lock : 1;
3919 } bits;
3920
3921 /**
3922 * Union for HW Lock flags.
3923 */
3924 uint8_t u8All;
3925 };
3926
3927 /**
3928 * Instances of HW to be locked.
3929 *
3930 * Note: If updating with more HW components, fields
3931 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3932 */
3933 struct dmub_hw_lock_inst_flags {
3934 /**
3935 * OTG HW instance for OTG master update lock.
3936 */
3937 uint8_t otg_inst;
3938 /**
3939 * OPP instance for cursor lock.
3940 */
3941 uint8_t opp_inst;
3942 /**
3943 * OTG HW instance for global update lock.
3944 * TODO: Remove, and re-use otg_inst.
3945 */
3946 uint8_t dig_inst;
3947 /**
3948 * Explicit pad to 4 byte boundary.
3949 */
3950 uint8_t pad;
3951 };
3952
3953 /**
3954 * Clients that can acquire the HW Lock Manager.
3955 *
3956 * Note: If updating with more clients, fields in
3957 * dmub_inbox0_cmd_lock_hw must be updated to match.
3958 */
3959 enum hw_lock_client {
3960 /**
3961 * Driver is the client of HW Lock Manager.
3962 */
3963 HW_LOCK_CLIENT_DRIVER = 0,
3964 /**
3965 * PSR SU is the client of HW Lock Manager.
3966 */
3967 HW_LOCK_CLIENT_PSR_SU = 1,
3968 HW_LOCK_CLIENT_SUBVP = 3,
3969 /**
3970 * Replay is the client of HW Lock Manager.
3971 */
3972 HW_LOCK_CLIENT_REPLAY = 4,
3973 HW_LOCK_CLIENT_FAMS2 = 5,
3974 /**
3975 * Invalid client.
3976 */
3977 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
3978 };
3979
3980 /**
3981 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3982 */
3983 struct dmub_cmd_lock_hw_data {
3984 /**
3985 * Specifies the client accessing HW Lock Manager.
3986 */
3987 enum hw_lock_client client;
3988 /**
3989 * HW instances to be locked.
3990 */
3991 struct dmub_hw_lock_inst_flags inst_flags;
3992 /**
3993 * Which components to be locked.
3994 */
3995 union dmub_hw_lock_flags hw_locks;
3996 /**
3997 * Specifies lock/unlock.
3998 */
3999 uint8_t lock;
4000 /**
4001 * HW can be unlocked separately from releasing the HW Lock Mgr.
4002 * This flag is set if the client wishes to release the object.
4003 */
4004 uint8_t should_release;
4005 /**
4006 * Explicit padding to 4 byte boundary.
4007 */
4008 uint8_t pad;
4009 };
4010
4011 /**
4012 * Definition of a DMUB_CMD__HW_LOCK command.
4013 * Command is used by driver and FW.
4014 */
4015 struct dmub_rb_cmd_lock_hw {
4016 /**
4017 * Command header.
4018 */
4019 struct dmub_cmd_header header;
4020 /**
4021 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
4022 */
4023 struct dmub_cmd_lock_hw_data lock_hw_data;
4024 };
4025
4026 /**
4027 * ABM command sub-types.
4028 */
4029 enum dmub_cmd_abm_type {
4030 /**
4031 * Initialize parameters for ABM algorithm.
4032 * Data is passed through an indirect buffer.
4033 */
4034 DMUB_CMD__ABM_INIT_CONFIG = 0,
4035 /**
4036 * Set OTG and panel HW instance.
4037 */
4038 DMUB_CMD__ABM_SET_PIPE = 1,
4039 /**
4040 * Set user requested backklight level.
4041 */
4042 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
4043 /**
4044 * Set ABM operating/aggression level.
4045 */
4046 DMUB_CMD__ABM_SET_LEVEL = 3,
4047 /**
4048 * Set ambient light level.
4049 */
4050 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
4051 /**
4052 * Enable/disable fractional duty cycle for backlight PWM.
4053 */
4054 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
4055
4056 /**
4057 * unregister vertical interrupt after steady state is reached
4058 */
4059 DMUB_CMD__ABM_PAUSE = 6,
4060
4061 /**
4062 * Save and Restore ABM state. On save we save parameters, and
4063 * on restore we update state with passed in data.
4064 */
4065 DMUB_CMD__ABM_SAVE_RESTORE = 7,
4066
4067 /**
4068 * Query ABM caps.
4069 */
4070 DMUB_CMD__ABM_QUERY_CAPS = 8,
4071
4072 /**
4073 * Set ABM Events
4074 */
4075 DMUB_CMD__ABM_SET_EVENT = 9,
4076
4077 /**
4078 * Get the current ACE curve.
4079 */
4080 DMUB_CMD__ABM_GET_ACE_CURVE = 10,
4081 };
4082
4083 struct abm_ace_curve {
4084 /**
4085 * @offsets: ACE curve offsets.
4086 */
4087 uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4088
4089 /**
4090 * @thresholds: ACE curve thresholds.
4091 */
4092 uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4093
4094 /**
4095 * @slopes: ACE curve slopes.
4096 */
4097 uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS];
4098 };
4099
4100 struct fixed_pt_format {
4101 /**
4102 * @sign_bit: Indicates whether one bit is reserved for the sign.
4103 */
4104 bool sign_bit;
4105
4106 /**
4107 * @num_int_bits: Number of bits used for integer part.
4108 */
4109 uint8_t num_int_bits;
4110
4111 /**
4112 * @num_frac_bits: Number of bits used for fractional part.
4113 */
4114 uint8_t num_frac_bits;
4115
4116 /**
4117 * @pad: Explicit padding to 4 byte boundary.
4118 */
4119 uint8_t pad;
4120 };
4121
4122 struct abm_caps {
4123 /**
4124 * @num_hg_bins: Number of histogram bins.
4125 */
4126 uint8_t num_hg_bins;
4127
4128 /**
4129 * @num_ace_segments: Number of ACE curve segments.
4130 */
4131 uint8_t num_ace_segments;
4132
4133 /**
4134 * @pad: Explicit padding to 4 byte boundary.
4135 */
4136 uint8_t pad[2];
4137
4138 /**
4139 * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0.
4140 */
4141 struct fixed_pt_format ace_thresholds_format;
4142
4143 /**
4144 * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0.
4145 */
4146 struct fixed_pt_format ace_offsets_format;
4147
4148 /**
4149 * @ace_slopes_format: Format of the ACE slopes.
4150 */
4151 struct fixed_pt_format ace_slopes_format;
4152 };
4153
4154 /**
4155 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
4156 * Requirements:
4157 * - Padded explicitly to 32-bit boundary.
4158 * - Must ensure this structure matches the one on driver-side,
4159 * otherwise it won't be aligned.
4160 */
4161 struct abm_config_table {
4162 /**
4163 * Gamma curve thresholds, used for crgb conversion.
4164 */
4165 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
4166 /**
4167 * Gamma curve offsets, used for crgb conversion.
4168 */
4169 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
4170 /**
4171 * Gamma curve slopes, used for crgb conversion.
4172 */
4173 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
4174 /**
4175 * Custom backlight curve thresholds.
4176 */
4177 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
4178 /**
4179 * Custom backlight curve offsets.
4180 */
4181 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
4182 /**
4183 * Ambient light thresholds.
4184 */
4185 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
4186 /**
4187 * Minimum programmable backlight.
4188 */
4189 uint16_t min_abm_backlight; // 122B
4190 /**
4191 * Minimum reduction values.
4192 */
4193 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
4194 /**
4195 * Maximum reduction values.
4196 */
4197 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
4198 /**
4199 * Bright positive gain.
4200 */
4201 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
4202 /**
4203 * Dark negative gain.
4204 */
4205 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
4206 /**
4207 * Hybrid factor.
4208 */
4209 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
4210 /**
4211 * Contrast factor.
4212 */
4213 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
4214 /**
4215 * Deviation gain.
4216 */
4217 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
4218 /**
4219 * Minimum knee.
4220 */
4221 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
4222 /**
4223 * Maximum knee.
4224 */
4225 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
4226 /**
4227 * Unused.
4228 */
4229 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
4230 /**
4231 * Explicit padding to 4 byte boundary.
4232 */
4233 uint8_t pad3[3]; // 229B
4234 /**
4235 * Backlight ramp reduction.
4236 */
4237 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
4238 /**
4239 * Backlight ramp start.
4240 */
4241 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
4242 };
4243
4244 /**
4245 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
4246 */
4247 struct dmub_cmd_abm_set_pipe_data {
4248 /**
4249 * OTG HW instance.
4250 */
4251 uint8_t otg_inst;
4252
4253 /**
4254 * Panel Control HW instance.
4255 */
4256 uint8_t panel_inst;
4257
4258 /**
4259 * Controls how ABM will interpret a set pipe or set level command.
4260 */
4261 uint8_t set_pipe_option;
4262
4263 /**
4264 * Unused.
4265 * TODO: Remove.
4266 */
4267 uint8_t ramping_boundary;
4268
4269 /**
4270 * PwrSeq HW Instance.
4271 */
4272 uint8_t pwrseq_inst;
4273
4274 /**
4275 * Explicit padding to 4 byte boundary.
4276 */
4277 uint8_t pad[3];
4278 };
4279
4280 /**
4281 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
4282 */
4283 struct dmub_rb_cmd_abm_set_pipe {
4284 /**
4285 * Command header.
4286 */
4287 struct dmub_cmd_header header;
4288
4289 /**
4290 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
4291 */
4292 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
4293 };
4294
4295 /**
4296 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
4297 */
4298 struct dmub_cmd_abm_set_backlight_data {
4299 /**
4300 * Number of frames to ramp to backlight user level.
4301 */
4302 uint32_t frame_ramp;
4303
4304 /**
4305 * Requested backlight level from user.
4306 */
4307 uint32_t backlight_user_level;
4308
4309 /**
4310 * ABM control version.
4311 */
4312 uint8_t version;
4313
4314 /**
4315 * Panel Control HW instance mask.
4316 * Bit 0 is Panel Control HW instance 0.
4317 * Bit 1 is Panel Control HW instance 1.
4318 */
4319 uint8_t panel_mask;
4320
4321 /**
4322 * Explicit padding to 4 byte boundary.
4323 */
4324 uint8_t pad[2];
4325 };
4326
4327 /**
4328 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
4329 */
4330 struct dmub_rb_cmd_abm_set_backlight {
4331 /**
4332 * Command header.
4333 */
4334 struct dmub_cmd_header header;
4335
4336 /**
4337 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
4338 */
4339 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
4340 };
4341
4342 /**
4343 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
4344 */
4345 struct dmub_cmd_abm_set_level_data {
4346 /**
4347 * Set current ABM operating/aggression level.
4348 */
4349 uint32_t level;
4350
4351 /**
4352 * ABM control version.
4353 */
4354 uint8_t version;
4355
4356 /**
4357 * Panel Control HW instance mask.
4358 * Bit 0 is Panel Control HW instance 0.
4359 * Bit 1 is Panel Control HW instance 1.
4360 */
4361 uint8_t panel_mask;
4362
4363 /**
4364 * Explicit padding to 4 byte boundary.
4365 */
4366 uint8_t pad[2];
4367 };
4368
4369 /**
4370 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
4371 */
4372 struct dmub_rb_cmd_abm_set_level {
4373 /**
4374 * Command header.
4375 */
4376 struct dmub_cmd_header header;
4377
4378 /**
4379 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
4380 */
4381 struct dmub_cmd_abm_set_level_data abm_set_level_data;
4382 };
4383
4384 /**
4385 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4386 */
4387 struct dmub_cmd_abm_set_ambient_level_data {
4388 /**
4389 * Ambient light sensor reading from OS.
4390 */
4391 uint32_t ambient_lux;
4392
4393 /**
4394 * ABM control version.
4395 */
4396 uint8_t version;
4397
4398 /**
4399 * Panel Control HW instance mask.
4400 * Bit 0 is Panel Control HW instance 0.
4401 * Bit 1 is Panel Control HW instance 1.
4402 */
4403 uint8_t panel_mask;
4404
4405 /**
4406 * Explicit padding to 4 byte boundary.
4407 */
4408 uint8_t pad[2];
4409 };
4410
4411 /**
4412 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4413 */
4414 struct dmub_rb_cmd_abm_set_ambient_level {
4415 /**
4416 * Command header.
4417 */
4418 struct dmub_cmd_header header;
4419
4420 /**
4421 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4422 */
4423 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
4424 };
4425
4426 /**
4427 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
4428 */
4429 struct dmub_cmd_abm_set_pwm_frac_data {
4430 /**
4431 * Enable/disable fractional duty cycle for backlight PWM.
4432 * TODO: Convert to uint8_t.
4433 */
4434 uint32_t fractional_pwm;
4435
4436 /**
4437 * ABM control version.
4438 */
4439 uint8_t version;
4440
4441 /**
4442 * Panel Control HW instance mask.
4443 * Bit 0 is Panel Control HW instance 0.
4444 * Bit 1 is Panel Control HW instance 1.
4445 */
4446 uint8_t panel_mask;
4447
4448 /**
4449 * Explicit padding to 4 byte boundary.
4450 */
4451 uint8_t pad[2];
4452 };
4453
4454 /**
4455 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
4456 */
4457 struct dmub_rb_cmd_abm_set_pwm_frac {
4458 /**
4459 * Command header.
4460 */
4461 struct dmub_cmd_header header;
4462
4463 /**
4464 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
4465 */
4466 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
4467 };
4468
4469 /**
4470 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4471 */
4472 struct dmub_cmd_abm_init_config_data {
4473 /**
4474 * Location of indirect buffer used to pass init data to ABM.
4475 */
4476 union dmub_addr src;
4477
4478 /**
4479 * Indirect buffer length.
4480 */
4481 uint16_t bytes;
4482
4483
4484 /**
4485 * ABM control version.
4486 */
4487 uint8_t version;
4488
4489 /**
4490 * Panel Control HW instance mask.
4491 * Bit 0 is Panel Control HW instance 0.
4492 * Bit 1 is Panel Control HW instance 1.
4493 */
4494 uint8_t panel_mask;
4495
4496 /**
4497 * Explicit padding to 4 byte boundary.
4498 */
4499 uint8_t pad[2];
4500 };
4501
4502 /**
4503 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
4504 */
4505 struct dmub_rb_cmd_abm_init_config {
4506 /**
4507 * Command header.
4508 */
4509 struct dmub_cmd_header header;
4510
4511 /**
4512 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4513 */
4514 struct dmub_cmd_abm_init_config_data abm_init_config_data;
4515 };
4516
4517 /**
4518 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
4519 */
4520
4521 struct dmub_cmd_abm_pause_data {
4522
4523 /**
4524 * Panel Control HW instance mask.
4525 * Bit 0 is Panel Control HW instance 0.
4526 * Bit 1 is Panel Control HW instance 1.
4527 */
4528 uint8_t panel_mask;
4529
4530 /**
4531 * OTG hw instance
4532 */
4533 uint8_t otg_inst;
4534
4535 /**
4536 * Enable or disable ABM pause
4537 */
4538 uint8_t enable;
4539
4540 /**
4541 * Explicit padding to 4 byte boundary.
4542 */
4543 uint8_t pad[1];
4544 };
4545
4546 /**
4547 * Definition of a DMUB_CMD__ABM_PAUSE command.
4548 */
4549 struct dmub_rb_cmd_abm_pause {
4550 /**
4551 * Command header.
4552 */
4553 struct dmub_cmd_header header;
4554
4555 /**
4556 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
4557 */
4558 struct dmub_cmd_abm_pause_data abm_pause_data;
4559 };
4560
4561 /**
4562 * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command.
4563 */
4564 struct dmub_cmd_abm_query_caps_in {
4565 /**
4566 * Panel instance.
4567 */
4568 uint8_t panel_inst;
4569
4570 /**
4571 * Explicit padding to 4 byte boundary.
4572 */
4573 uint8_t pad[3];
4574 };
4575
4576 /**
4577 * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command.
4578 */
4579 struct dmub_cmd_abm_query_caps_out {
4580 /**
4581 * SW Algorithm caps.
4582 */
4583 struct abm_caps sw_caps;
4584
4585 /**
4586 * ABM HW caps.
4587 */
4588 struct abm_caps hw_caps;
4589 };
4590
4591 /**
4592 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
4593 */
4594 struct dmub_rb_cmd_abm_query_caps {
4595 /**
4596 * Command header.
4597 */
4598 struct dmub_cmd_header header;
4599
4600 /**
4601 * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command.
4602 */
4603 union {
4604 struct dmub_cmd_abm_query_caps_in abm_query_caps_in;
4605 struct dmub_cmd_abm_query_caps_out abm_query_caps_out;
4606 } data;
4607 };
4608
4609 /**
4610 * enum dmub_abm_ace_curve_type - ACE curve type.
4611 */
4612 enum dmub_abm_ace_curve_type {
4613 /**
4614 * ACE curve as defined by the SW layer.
4615 */
4616 ABM_ACE_CURVE_TYPE__SW = 0,
4617 /**
4618 * ACE curve as defined by the SW to HW translation interface layer.
4619 */
4620 ABM_ACE_CURVE_TYPE__SW_IF = 1,
4621 };
4622
4623 /**
4624 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
4625 */
4626 struct dmub_rb_cmd_abm_get_ace_curve {
4627 /**
4628 * Command header.
4629 */
4630 struct dmub_cmd_header header;
4631
4632 /**
4633 * Address where ACE curve should be copied.
4634 */
4635 union dmub_addr dest;
4636
4637 /**
4638 * Type of ACE curve being queried.
4639 */
4640 enum dmub_abm_ace_curve_type ace_type;
4641
4642 /**
4643 * Indirect buffer length.
4644 */
4645 uint16_t bytes;
4646
4647 /**
4648 * eDP panel instance.
4649 */
4650 uint8_t panel_inst;
4651
4652 /**
4653 * Explicit padding to 4 byte boundary.
4654 */
4655 uint8_t pad;
4656 };
4657
4658 /**
4659 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4660 */
4661 struct dmub_rb_cmd_abm_save_restore {
4662 /**
4663 * Command header.
4664 */
4665 struct dmub_cmd_header header;
4666
4667 /**
4668 * OTG hw instance
4669 */
4670 uint8_t otg_inst;
4671
4672 /**
4673 * Enable or disable ABM pause
4674 */
4675 uint8_t freeze;
4676
4677 /**
4678 * Explicit padding to 4 byte boundary.
4679 */
4680 uint8_t debug;
4681
4682 /**
4683 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
4684 */
4685 struct dmub_cmd_abm_init_config_data abm_init_config_data;
4686 };
4687
4688 /**
4689 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
4690 */
4691
4692 struct dmub_cmd_abm_set_event_data {
4693
4694 /**
4695 * VB Scaling Init. Strength Mapping
4696 * Byte 0: 0~255 for VB level 0
4697 * Byte 1: 0~255 for VB level 1
4698 * Byte 2: 0~255 for VB level 2
4699 * Byte 3: 0~255 for VB level 3
4700 */
4701 uint32_t vb_scaling_strength_mapping;
4702 /**
4703 * VariBright Scaling Enable
4704 */
4705 uint8_t vb_scaling_enable;
4706 /**
4707 * Panel Control HW instance mask.
4708 * Bit 0 is Panel Control HW instance 0.
4709 * Bit 1 is Panel Control HW instance 1.
4710 */
4711 uint8_t panel_mask;
4712
4713 /**
4714 * Explicit padding to 4 byte boundary.
4715 */
4716 uint8_t pad[2];
4717 };
4718
4719 /**
4720 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
4721 */
4722 struct dmub_rb_cmd_abm_set_event {
4723 /**
4724 * Command header.
4725 */
4726 struct dmub_cmd_header header;
4727
4728 /**
4729 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
4730 */
4731 struct dmub_cmd_abm_set_event_data abm_set_event_data;
4732 };
4733
4734 /**
4735 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
4736 */
4737 struct dmub_cmd_query_feature_caps_data {
4738 /**
4739 * DMUB feature capabilities.
4740 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
4741 */
4742 struct dmub_feature_caps feature_caps;
4743 };
4744
4745 /**
4746 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
4747 */
4748 struct dmub_rb_cmd_query_feature_caps {
4749 /**
4750 * Command header.
4751 */
4752 struct dmub_cmd_header header;
4753 /**
4754 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
4755 */
4756 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
4757 };
4758
4759 /**
4760 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4761 */
4762 struct dmub_cmd_visual_confirm_color_data {
4763 /**
4764 * DMUB visual confirm color
4765 */
4766 struct dmub_visual_confirm_color visual_confirm_color;
4767 };
4768
4769 /**
4770 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4771 */
4772 struct dmub_rb_cmd_get_visual_confirm_color {
4773 /**
4774 * Command header.
4775 */
4776 struct dmub_cmd_header header;
4777 /**
4778 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4779 */
4780 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
4781 };
4782
4783 /**
4784 * enum dmub_cmd_panel_cntl_type - Panel control command.
4785 */
4786 enum dmub_cmd_panel_cntl_type {
4787 /**
4788 * Initializes embedded panel hardware blocks.
4789 */
4790 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
4791 /**
4792 * Queries backlight info for the embedded panel.
4793 */
4794 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
4795 /**
4796 * Sets the PWM Freq as per user's requirement.
4797 */
4798 DMUB_CMD__PANEL_DEBUG_PWM_FREQ = 2,
4799 };
4800
4801 /**
4802 * struct dmub_cmd_panel_cntl_data - Panel control data.
4803 */
4804 struct dmub_cmd_panel_cntl_data {
4805 uint32_t pwrseq_inst; /**< pwrseq instance */
4806 uint32_t current_backlight; /* in/out */
4807 uint32_t bl_pwm_cntl; /* in/out */
4808 uint32_t bl_pwm_period_cntl; /* in/out */
4809 uint32_t bl_pwm_ref_div1; /* in/out */
4810 uint8_t is_backlight_on : 1; /* in/out */
4811 uint8_t is_powered_on : 1; /* in/out */
4812 uint8_t padding[3];
4813 uint32_t bl_pwm_ref_div2; /* in/out */
4814 uint8_t reserved[4];
4815 };
4816
4817 /**
4818 * struct dmub_rb_cmd_panel_cntl - Panel control command.
4819 */
4820 struct dmub_rb_cmd_panel_cntl {
4821 struct dmub_cmd_header header; /**< header */
4822 struct dmub_cmd_panel_cntl_data data; /**< payload */
4823 };
4824
4825 struct dmub_optc_state {
4826 uint32_t v_total_max;
4827 uint32_t v_total_min;
4828 uint32_t tg_inst;
4829 };
4830
4831 struct dmub_rb_cmd_drr_update {
4832 struct dmub_cmd_header header;
4833 struct dmub_optc_state dmub_optc_state_req;
4834 };
4835
4836 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
4837 uint32_t pix_clk_100hz;
4838 uint8_t max_ramp_step;
4839 uint8_t pipes;
4840 uint8_t min_refresh_in_hz;
4841 uint8_t pipe_count;
4842 uint8_t pipe_index[4];
4843 };
4844
4845 struct dmub_cmd_fw_assisted_mclk_switch_config {
4846 uint8_t fams_enabled;
4847 uint8_t visual_confirm_enabled;
4848 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
4849 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
4850 };
4851
4852 struct dmub_rb_cmd_fw_assisted_mclk_switch {
4853 struct dmub_cmd_header header;
4854 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
4855 };
4856
4857 /**
4858 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4859 */
4860 struct dmub_cmd_lvtma_control_data {
4861 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
4862 uint8_t bypass_panel_control_wait;
4863 uint8_t reserved_0[2]; /**< For future use */
4864 uint8_t pwrseq_inst; /**< LVTMA control instance */
4865 uint8_t reserved_1[3]; /**< For future use */
4866 };
4867
4868 /**
4869 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4870 */
4871 struct dmub_rb_cmd_lvtma_control {
4872 /**
4873 * Command header.
4874 */
4875 struct dmub_cmd_header header;
4876 /**
4877 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4878 */
4879 struct dmub_cmd_lvtma_control_data data;
4880 };
4881
4882 /**
4883 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4884 */
4885 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
4886 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
4887 uint8_t is_usb; /**< is phy is usb */
4888 uint8_t is_dp_alt_disable; /**< is dp alt disable */
4889 uint8_t is_dp4; /**< is dp in 4 lane */
4890 };
4891
4892 /**
4893 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4894 */
4895 struct dmub_rb_cmd_transmitter_query_dp_alt {
4896 struct dmub_cmd_header header; /**< header */
4897 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
4898 };
4899
4900 struct phy_test_mode {
4901 uint8_t mode;
4902 uint8_t pat0;
4903 uint8_t pad[2];
4904 };
4905
4906 /**
4907 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
4908 */
4909 struct dmub_rb_cmd_transmitter_set_phy_fsm_data {
4910 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
4911 uint8_t mode; /**< HDMI/DP/DP2 etc */
4912 uint8_t lane_num; /**< Number of lanes */
4913 uint32_t symclk_100Hz; /**< PLL symclock in 100hz */
4914 struct phy_test_mode test_mode;
4915 enum dmub_phy_fsm_state state;
4916 uint32_t status;
4917 uint8_t pad;
4918 };
4919
4920 /**
4921 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
4922 */
4923 struct dmub_rb_cmd_transmitter_set_phy_fsm {
4924 struct dmub_cmd_header header; /**< header */
4925 struct dmub_rb_cmd_transmitter_set_phy_fsm_data data; /**< payload */
4926 };
4927
4928 /**
4929 * Maximum number of bytes a chunk sent to DMUB for parsing
4930 */
4931 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
4932
4933 /**
4934 * Represent a chunk of CEA blocks sent to DMUB for parsing
4935 */
4936 struct dmub_cmd_send_edid_cea {
4937 uint16_t offset; /**< offset into the CEA block */
4938 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
4939 uint16_t cea_total_length; /**< total length of the CEA block */
4940 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
4941 uint8_t pad[3]; /**< padding and for future expansion */
4942 };
4943
4944 /**
4945 * Result of VSDB parsing from CEA block
4946 */
4947 struct dmub_cmd_edid_cea_amd_vsdb {
4948 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
4949 uint8_t freesync_supported; /**< 1 if Freesync is supported */
4950 uint16_t amd_vsdb_version; /**< AMD VSDB version */
4951 uint16_t min_frame_rate; /**< Maximum frame rate */
4952 uint16_t max_frame_rate; /**< Minimum frame rate */
4953 };
4954
4955 /**
4956 * Result of sending a CEA chunk
4957 */
4958 struct dmub_cmd_edid_cea_ack {
4959 uint16_t offset; /**< offset of the chunk into the CEA block */
4960 uint8_t success; /**< 1 if this sending of chunk succeeded */
4961 uint8_t pad; /**< padding and for future expansion */
4962 };
4963
4964 /**
4965 * Specify whether the result is an ACK/NACK or the parsing has finished
4966 */
4967 enum dmub_cmd_edid_cea_reply_type {
4968 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
4969 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
4970 };
4971
4972 /**
4973 * Definition of a DMUB_CMD__EDID_CEA command.
4974 */
4975 struct dmub_rb_cmd_edid_cea {
4976 struct dmub_cmd_header header; /**< Command header */
4977 union dmub_cmd_edid_cea_data {
4978 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
4979 struct dmub_cmd_edid_cea_output { /**< output with results */
4980 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
4981 union {
4982 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
4983 struct dmub_cmd_edid_cea_ack ack;
4984 };
4985 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
4986 } data; /**< Command data */
4987
4988 };
4989
4990 /**
4991 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
4992 */
4993 struct dmub_cmd_cable_id_input {
4994 uint8_t phy_inst; /**< phy inst for cable id data */
4995 };
4996
4997 /**
4998 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
4999 */
5000 struct dmub_cmd_cable_id_output {
5001 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
5002 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
5003 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
5004 uint8_t RESERVED :2; /**< reserved means not defined */
5005 };
5006
5007 /**
5008 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
5009 */
5010 struct dmub_rb_cmd_get_usbc_cable_id {
5011 struct dmub_cmd_header header; /**< Command header */
5012 /**
5013 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
5014 */
5015 union dmub_cmd_cable_id_data {
5016 struct dmub_cmd_cable_id_input input; /**< Input */
5017 struct dmub_cmd_cable_id_output output; /**< Output */
5018 uint8_t output_raw; /**< Raw data output */
5019 } data;
5020 };
5021
5022 /**
5023 * Command type of a DMUB_CMD__SECURE_DISPLAY command
5024 */
5025 enum dmub_cmd_secure_display_type {
5026 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
5027 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
5028 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
5029 };
5030
5031 /**
5032 * Definition of a DMUB_CMD__SECURE_DISPLAY command
5033 */
5034 struct dmub_rb_cmd_secure_display {
5035 struct dmub_cmd_header header;
5036 /**
5037 * Data passed from driver to dmub firmware.
5038 */
5039 struct dmub_cmd_roi_info {
5040 uint16_t x_start;
5041 uint16_t x_end;
5042 uint16_t y_start;
5043 uint16_t y_end;
5044 uint8_t otg_id;
5045 uint8_t phy_id;
5046 } roi_info;
5047 };
5048
5049 /**
5050 * Command type of a DMUB_CMD__PSP command
5051 */
5052 enum dmub_cmd_psp_type {
5053 DMUB_CMD__PSP_ASSR_ENABLE = 0
5054 };
5055
5056 /**
5057 * Data passed from driver to FW in a DMUB_CMD__PSP_ASSR_ENABLE command.
5058 */
5059 struct dmub_cmd_assr_enable_data {
5060 /**
5061 * ASSR enable or disable.
5062 */
5063 uint8_t enable;
5064 /**
5065 * PHY port type.
5066 * Indicates eDP / non-eDP port type
5067 */
5068 uint8_t phy_port_type;
5069 /**
5070 * PHY port ID.
5071 */
5072 uint8_t phy_port_id;
5073 /**
5074 * Link encoder index.
5075 */
5076 uint8_t link_enc_index;
5077 /**
5078 * HPO mode.
5079 */
5080 uint8_t hpo_mode;
5081
5082 /**
5083 * Reserved field.
5084 */
5085 uint8_t reserved[7];
5086 };
5087
5088 /**
5089 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
5090 */
5091 struct dmub_rb_cmd_assr_enable {
5092 /**
5093 * Command header.
5094 */
5095 struct dmub_cmd_header header;
5096
5097 /**
5098 * Assr data.
5099 */
5100 struct dmub_cmd_assr_enable_data assr_data;
5101
5102 /**
5103 * Reserved field.
5104 */
5105 uint32_t reserved[3];
5106 };
5107
5108 /**
5109 * union dmub_rb_cmd - DMUB inbox command.
5110 */
5111 union dmub_rb_cmd {
5112 /**
5113 * Elements shared with all commands.
5114 */
5115 struct dmub_rb_cmd_common cmd_common;
5116 /**
5117 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
5118 */
5119 struct dmub_rb_cmd_read_modify_write read_modify_write;
5120 /**
5121 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
5122 */
5123 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
5124 /**
5125 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
5126 */
5127 struct dmub_rb_cmd_burst_write burst_write;
5128 /**
5129 * Definition of a DMUB_CMD__REG_REG_WAIT command.
5130 */
5131 struct dmub_rb_cmd_reg_wait reg_wait;
5132 /**
5133 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
5134 */
5135 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
5136 /**
5137 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
5138 */
5139 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
5140 /**
5141 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
5142 */
5143 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
5144 /**
5145 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
5146 */
5147 struct dmub_rb_cmd_dpphy_init dpphy_init;
5148 /**
5149 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
5150 */
5151 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
5152 /**
5153 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
5154 */
5155 struct dmub_rb_cmd_domain_control domain_control;
5156 /**
5157 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
5158 */
5159 struct dmub_rb_cmd_psr_set_version psr_set_version;
5160 /**
5161 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
5162 */
5163 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
5164 /**
5165 * Definition of a DMUB_CMD__PSR_ENABLE command.
5166 */
5167 struct dmub_rb_cmd_psr_enable psr_enable;
5168 /**
5169 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
5170 */
5171 struct dmub_rb_cmd_psr_set_level psr_set_level;
5172 /**
5173 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
5174 */
5175 struct dmub_rb_cmd_psr_force_static psr_force_static;
5176 /**
5177 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
5178 */
5179 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
5180 /**
5181 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
5182 */
5183 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
5184 /**
5185 * Definition of a DMUB_CMD__HW_LOCK command.
5186 * Command is used by driver and FW.
5187 */
5188 struct dmub_rb_cmd_lock_hw lock_hw;
5189 /**
5190 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
5191 */
5192 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
5193 /**
5194 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
5195 */
5196 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
5197 /**
5198 * Definition of a DMUB_CMD__PLAT_54186_WA command.
5199 */
5200 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
5201 /**
5202 * Definition of a DMUB_CMD__MALL command.
5203 */
5204 struct dmub_rb_cmd_mall mall;
5205
5206 /**
5207 * Definition of a DMUB_CMD__CAB command.
5208 */
5209 struct dmub_rb_cmd_cab_for_ss cab;
5210
5211 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
5212
5213 /**
5214 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
5215 */
5216 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
5217
5218 /**
5219 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
5220 */
5221 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
5222
5223 /**
5224 * Definition of DMUB_CMD__PANEL_CNTL commands.
5225 */
5226 struct dmub_rb_cmd_panel_cntl panel_cntl;
5227
5228 /**
5229 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
5230 */
5231 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
5232
5233 /**
5234 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
5235 */
5236 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
5237
5238 /**
5239 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
5240 */
5241 struct dmub_rb_cmd_abm_set_level abm_set_level;
5242
5243 /**
5244 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
5245 */
5246 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
5247
5248 /**
5249 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
5250 */
5251 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
5252
5253 /**
5254 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
5255 */
5256 struct dmub_rb_cmd_abm_init_config abm_init_config;
5257
5258 /**
5259 * Definition of a DMUB_CMD__ABM_PAUSE command.
5260 */
5261 struct dmub_rb_cmd_abm_pause abm_pause;
5262
5263 /**
5264 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
5265 */
5266 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
5267
5268 /**
5269 * Definition of a DMUB_CMD__ABM_QUERY_CAPS command.
5270 */
5271 struct dmub_rb_cmd_abm_query_caps abm_query_caps;
5272
5273 /**
5274 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
5275 */
5276 struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;
5277
5278 /**
5279 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
5280 */
5281 struct dmub_rb_cmd_abm_set_event abm_set_event;
5282
5283 /**
5284 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
5285 */
5286 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
5287
5288 /**
5289 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
5290 */
5291 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
5292
5293 /**
5294 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
5295 */
5296 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
5297
5298 /**
5299 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
5300 */
5301 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
5302 struct dmub_rb_cmd_drr_update drr_update;
5303 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
5304
5305 /**
5306 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
5307 */
5308 struct dmub_rb_cmd_lvtma_control lvtma_control;
5309 /**
5310 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
5311 */
5312 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
5313 /**
5314 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_SET_PHY_FSM command.
5315 */
5316 struct dmub_rb_cmd_transmitter_set_phy_fsm set_phy_fsm;
5317 /**
5318 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
5319 */
5320 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
5321 /**
5322 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
5323 */
5324 struct dmub_rb_cmd_set_config_access set_config_access;
5325 /**
5326 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
5327 */
5328 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
5329 /**
5330 * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command.
5331 */
5332 struct dmub_rb_cmd_set_tps_notification set_tps_notification;
5333 /**
5334 * Definition of a DMUB_CMD__EDID_CEA command.
5335 */
5336 struct dmub_rb_cmd_edid_cea edid_cea;
5337 /**
5338 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
5339 */
5340 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
5341
5342 /**
5343 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
5344 */
5345 struct dmub_rb_cmd_query_hpd_state query_hpd;
5346 /**
5347 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
5348 */
5349 struct dmub_rb_cmd_secure_display secure_display;
5350
5351 /**
5352 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
5353 */
5354 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
5355 /**
5356 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
5357 */
5358 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
5359 /**
5360 * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command.
5361 */
5362 struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state;
5363 /*
5364 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
5365 */
5366 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
5367 /**
5368 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
5369 */
5370 struct dmub_rb_cmd_replay_enable replay_enable;
5371 /**
5372 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
5373 */
5374 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
5375 /**
5376 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
5377 */
5378 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
5379 /**
5380 * Definition of a DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL command.
5381 */
5382 struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal replay_set_power_opt_and_coasting_vtotal;
5383
5384 struct dmub_rb_cmd_replay_set_timing_sync replay_set_timing_sync;
5385 /**
5386 * Definition of a DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
5387 */
5388 struct dmub_rb_cmd_replay_set_frameupdate_timer replay_set_frameupdate_timer;
5389 /**
5390 * Definition of a DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL command.
5391 */
5392 struct dmub_rb_cmd_replay_set_pseudo_vtotal replay_set_pseudo_vtotal;
5393 /**
5394 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
5395 */
5396 struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;
5397 /**
5398 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
5399 */
5400 struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;
5401 /**
5402 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
5403 */
5404 struct dmub_rb_cmd_assr_enable assr_enable;
5405 struct dmub_rb_cmd_fams2 fams2_config;
5406
5407 struct dmub_rb_cmd_fams2_drr_update fams2_drr_update;
5408
5409 struct dmub_rb_cmd_fams2_flip fams2_flip;
5410 };
5411
5412 /**
5413 * union dmub_rb_out_cmd - Outbox command
5414 */
5415 union dmub_rb_out_cmd {
5416 /**
5417 * Parameters common to every command.
5418 */
5419 struct dmub_rb_cmd_common cmd_common;
5420 /**
5421 * AUX reply command.
5422 */
5423 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
5424 /**
5425 * HPD notify command.
5426 */
5427 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
5428 /**
5429 * SET_CONFIG reply command.
5430 */
5431 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
5432 /**
5433 * DPIA notification command.
5434 */
5435 struct dmub_rb_cmd_dpia_notification dpia_notification;
5436 /**
5437 * HPD sense notification command.
5438 */
5439 struct dmub_rb_cmd_hpd_sense_notify hpd_sense_notify;
5440 };
5441 #pragma pack(pop)
5442
5443
5444 //==============================================================================
5445 //</DMUB_CMD>===================================================================
5446 //==============================================================================
5447 //< DMUB_RB>====================================================================
5448 //==============================================================================
5449
5450 /**
5451 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
5452 */
5453 struct dmub_rb_init_params {
5454 void *ctx; /**< Caller provided context pointer */
5455 void *base_address; /**< CPU base address for ring's data */
5456 uint32_t capacity; /**< Ringbuffer capacity in bytes */
5457 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
5458 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
5459 };
5460
5461 /**
5462 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
5463 */
5464 struct dmub_rb {
5465 void *base_address; /**< CPU address for the ring's data */
5466 uint32_t rptr; /**< Read pointer for consumer in bytes */
5467 uint32_t wrpt; /**< Write pointer for producer in bytes */
5468 uint32_t capacity; /**< Ringbuffer capacity in bytes */
5469
5470 void *ctx; /**< Caller provided context pointer */
5471 void *dmub; /**< Pointer to the DMUB interface */
5472 };
5473
5474 /**
5475 * @brief Checks if the ringbuffer is empty.
5476 *
5477 * @param rb DMUB Ringbuffer
5478 * @return true if empty
5479 * @return false otherwise
5480 */
dmub_rb_empty(struct dmub_rb * rb)5481 static inline bool dmub_rb_empty(struct dmub_rb *rb)
5482 {
5483 return (rb->wrpt == rb->rptr);
5484 }
5485
5486 /**
5487 * @brief Checks if the ringbuffer is full
5488 *
5489 * @param rb DMUB Ringbuffer
5490 * @return true if full
5491 * @return false otherwise
5492 */
dmub_rb_full(struct dmub_rb * rb)5493 static inline bool dmub_rb_full(struct dmub_rb *rb)
5494 {
5495 uint32_t data_count;
5496
5497 if (rb->wrpt >= rb->rptr)
5498 data_count = rb->wrpt - rb->rptr;
5499 else
5500 data_count = rb->capacity - (rb->rptr - rb->wrpt);
5501
5502 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
5503 }
5504
5505 /**
5506 * @brief Pushes a command into the ringbuffer
5507 *
5508 * @param rb DMUB ringbuffer
5509 * @param cmd The command to push
5510 * @return true if the ringbuffer was not full
5511 * @return false otherwise
5512 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)5513 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
5514 const union dmub_rb_cmd *cmd)
5515 {
5516 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
5517 const uint64_t *src = (const uint64_t *)cmd;
5518 uint8_t i;
5519
5520 if (dmub_rb_full(rb))
5521 return false;
5522
5523 // copying data
5524 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5525 *dst++ = *src++;
5526
5527 rb->wrpt += DMUB_RB_CMD_SIZE;
5528
5529 if (rb->wrpt >= rb->capacity)
5530 rb->wrpt %= rb->capacity;
5531
5532 return true;
5533 }
5534
5535 /**
5536 * @brief Pushes a command into the DMUB outbox ringbuffer
5537 *
5538 * @param rb DMUB outbox ringbuffer
5539 * @param cmd Outbox command
5540 * @return true if not full
5541 * @return false otherwise
5542 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)5543 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
5544 const union dmub_rb_out_cmd *cmd)
5545 {
5546 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
5547 const uint8_t *src = (const uint8_t *)cmd;
5548
5549 if (dmub_rb_full(rb))
5550 return false;
5551
5552 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
5553
5554 rb->wrpt += DMUB_RB_CMD_SIZE;
5555
5556 if (rb->wrpt >= rb->capacity)
5557 rb->wrpt %= rb->capacity;
5558
5559 return true;
5560 }
5561
5562 /**
5563 * @brief Returns the next unprocessed command in the ringbuffer.
5564 *
5565 * @param rb DMUB ringbuffer
5566 * @param cmd The command to return
5567 * @return true if not empty
5568 * @return false otherwise
5569 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)5570 static inline bool dmub_rb_front(struct dmub_rb *rb,
5571 union dmub_rb_cmd **cmd)
5572 {
5573 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
5574
5575 if (dmub_rb_empty(rb))
5576 return false;
5577
5578 *cmd = (union dmub_rb_cmd *)rb_cmd;
5579
5580 return true;
5581 }
5582
5583 /**
5584 * @brief Determines the next ringbuffer offset.
5585 *
5586 * @param rb DMUB inbox ringbuffer
5587 * @param num_cmds Number of commands
5588 * @param next_rptr The next offset in the ringbuffer
5589 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)5590 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
5591 uint32_t num_cmds,
5592 uint32_t *next_rptr)
5593 {
5594 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
5595
5596 if (*next_rptr >= rb->capacity)
5597 *next_rptr %= rb->capacity;
5598 }
5599
5600 /**
5601 * @brief Returns a pointer to a command in the inbox.
5602 *
5603 * @param rb DMUB inbox ringbuffer
5604 * @param cmd The inbox command to return
5605 * @param rptr The ringbuffer offset
5606 * @return true if not empty
5607 * @return false otherwise
5608 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)5609 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
5610 union dmub_rb_cmd **cmd,
5611 uint32_t rptr)
5612 {
5613 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
5614
5615 if (dmub_rb_empty(rb))
5616 return false;
5617
5618 *cmd = (union dmub_rb_cmd *)rb_cmd;
5619
5620 return true;
5621 }
5622
5623 /**
5624 * @brief Returns the next unprocessed command in the outbox.
5625 *
5626 * @param rb DMUB outbox ringbuffer
5627 * @param cmd The outbox command to return
5628 * @return true if not empty
5629 * @return false otherwise
5630 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)5631 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
5632 union dmub_rb_out_cmd *cmd)
5633 {
5634 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
5635 uint64_t *dst = (uint64_t *)cmd;
5636 uint8_t i;
5637
5638 if (dmub_rb_empty(rb))
5639 return false;
5640
5641 // copying data
5642 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5643 *dst++ = *src++;
5644
5645 return true;
5646 }
5647
5648 /**
5649 * @brief Removes the front entry in the ringbuffer.
5650 *
5651 * @param rb DMUB ringbuffer
5652 * @return true if the command was removed
5653 * @return false if there were no commands
5654 */
dmub_rb_pop_front(struct dmub_rb * rb)5655 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
5656 {
5657 if (dmub_rb_empty(rb))
5658 return false;
5659
5660 rb->rptr += DMUB_RB_CMD_SIZE;
5661
5662 if (rb->rptr >= rb->capacity)
5663 rb->rptr %= rb->capacity;
5664
5665 return true;
5666 }
5667
5668 /**
5669 * @brief Flushes commands in the ringbuffer to framebuffer memory.
5670 *
5671 * Avoids a race condition where DMCUB accesses memory while
5672 * there are still writes in flight to framebuffer.
5673 *
5674 * @param rb DMUB ringbuffer
5675 */
dmub_rb_flush_pending(const struct dmub_rb * rb)5676 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
5677 {
5678 uint32_t rptr = rb->rptr;
5679 uint32_t wptr = rb->wrpt;
5680
5681 while (rptr != wptr) {
5682 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
5683 uint8_t i;
5684
5685 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
5686 (void)READ_ONCE(*data++);
5687
5688 rptr += DMUB_RB_CMD_SIZE;
5689 if (rptr >= rb->capacity)
5690 rptr %= rb->capacity;
5691 }
5692 }
5693
5694 /**
5695 * @brief Initializes a DMCUB ringbuffer
5696 *
5697 * @param rb DMUB ringbuffer
5698 * @param init_params initial configuration for the ringbuffer
5699 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)5700 static inline void dmub_rb_init(struct dmub_rb *rb,
5701 struct dmub_rb_init_params *init_params)
5702 {
5703 rb->base_address = init_params->base_address;
5704 rb->capacity = init_params->capacity;
5705 rb->rptr = init_params->read_ptr;
5706 rb->wrpt = init_params->write_ptr;
5707 }
5708
5709 /**
5710 * @brief Copies output data from in/out commands into the given command.
5711 *
5712 * @param rb DMUB ringbuffer
5713 * @param cmd Command to copy data into
5714 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)5715 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
5716 union dmub_rb_cmd *cmd)
5717 {
5718 // Copy rb entry back into command
5719 uint8_t *rd_ptr = (rb->rptr == 0) ?
5720 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
5721 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
5722
5723 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
5724 }
5725
5726 //==============================================================================
5727 //</DMUB_RB>====================================================================
5728 //==============================================================================
5729 #endif /* _DMUB_CMD_H_ */
5730