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Searched refs:PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT (Results 1 – 15 of 15) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gca/
Dgfx_6_0_sh_mask.h6877 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0x0000000a macro
Dgfx_7_2_sh_mask.h5790 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa macro
Dgfx_8_0_sh_mask.h6578 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa macro
Dgfx_8_1_sh_mask.h7112 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT 0xa macro
/openbsd/src/sys/dev/pci/drm/amd/include/asic_reg/gc/
Dgc_9_0_sh_mask.h21487 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_9_4_3_sh_mask.h24932 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_9_1_sh_mask.h22794 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_9_2_1_sh_mask.h22737 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_9_4_2_sh_mask.h16552 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_11_5_0_sh_mask.h27484 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_11_0_0_sh_mask.h31635 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_12_0_0_sh_mask.h35612 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_11_0_3_sh_mask.h34133 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_10_1_0_sh_mask.h31382 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro
Dgc_10_3_0_sh_mask.h29750 #define PA_SU_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT … macro