Home
last modified time | relevance | path

Searched refs:PACKET3_WAIT_REG_MEM (Results 1 – 24 of 24) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dsi_enums.h209 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dsoc15d.h141 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dnvd.h116 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dvid.h168 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dcikd.h287 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dgfx_v7_0.c2079 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_hdp_flush()
3103 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_pipeline_sync()
3146 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_ring_emit_vm_flush()
4932 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v7_0_wait_reg_mem()
Dsid.h1719 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dgfx_v8_0.c6066 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_hdp_flush()
6199 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_pipeline_sync()
6218 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_ring_emit_vm_flush()
6397 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v8_0_wait_reg_mem()
Dgfx_v6_0.c2270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_pipeline_sync()
2297 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v6_0_ring_emit_vm_flush()
Dgfx_v9_4_3.c403 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_4_3_wait_reg_mem()
Dgfx_v12_0.c386 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v12_0_wait_reg_mem()
Dgfx_v9_0.c1150 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v9_0_wait_reg_mem()
Dgfx_v11_0.c467 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v11_0_wait_reg_mem()
Dgfx_v10_0.c3928 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in gfx_v10_0_wait_reg_mem()
/openbsd/src/sys/dev/pci/drm/radeon/
Dnid.h1194 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dr600_cs.c843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) { in r600_cs_common_vline_parse()
1751 case PACKET3_WAIT_REG_MEM: in r600_packet3_check()
Dsid.h1656 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dcikd.h1755 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dsi.c4549 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_gfx_check()
4652 case PACKET3_WAIT_REG_MEM: in si_vm_packet3_compute_check()
5091 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in si_vm_flush()
Devergreen_cs.c2087 case PACKET3_WAIT_REG_MEM: in evergreen_packet3_check()
3390 case PACKET3_WAIT_REG_MEM: in evergreen_vm_packet3_check()
Devergreend.h1578 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dni.c2678 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
Dr600d.h1615 #define PACKET3_WAIT_REG_MEM 0x3C macro
Dcik.c3520 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
5733 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()