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Searched refs:PACKET3_PREAMBLE_END_CLEAR_STATE (Results 1 – 20 of 20) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dsi_enums.h254 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dsoc15d.h217 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dnvd.h207 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dvid.h270 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dcikd.h388 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dsid.h1840 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dgfx_v6_0.c2032 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_cp_gfx_start()
2873 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v6_0_get_csb_buffer()
Dgfx_v7_0.c2503 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_cp_gfx_start()
3936 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v7_0_get_csb_buffer()
Dgfx_v8_0.c1248 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_get_csb_buffer()
4184 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v8_0_cp_gfx_start()
Dgfx_v9_0.c1648 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_get_csb_buffer()
3314 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v9_0_cp_gfx_start()
Dgfx_v11_0.c846 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v11_0_get_csb_buffer()
3468 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v11_0_cp_gfx_start()
Dgfx_v10_0.c4274 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_get_csb_buffer()
6259 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in gfx_v10_0_cp_gfx_start()
/openbsd/src/sys/dev/pci/drm/radeon/
Dnid.h1263 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dsid.h1777 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dcikd.h1855 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Devergreend.h1658 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) macro
Dni.c1559 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
Dsi.c3579 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in si_cp_start()
5749 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in si_get_csb_buffer()
Dcik.c4007 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
6758 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_get_csb_buffer()
Devergreen.c3033 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in evergreen_cp_start()