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/openbsd/src/gnu/llvm/llvm/lib/DebugInfo/DWARF/
DDWARFExpression.cpp25 typedef DWARFExpression::Operation Op; in getDescriptions() typedef
26 typedef Op::Description Desc; in getDescriptions()
29 Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr); in getDescriptions()
30 Descriptions[DW_OP_deref] = Desc(Op::Dwarf2); in getDescriptions()
31 Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1); in getDescriptions()
32 Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1); in getDescriptions()
33 Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2); in getDescriptions()
34 Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2); in getDescriptions()
35 Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4); in getDescriptions()
36 Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4); in getDescriptions()
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/openbsd/src/gnu/llvm/llvm/lib/Target/VE/
DVVPISelLowering.cpp21 SDValue VETargetLowering::splitMaskArithmetic(SDValue Op, in splitMaskArithmetic() argument
23 VECustomDAG CDAG(DAG, Op); in splitMaskArithmetic()
25 CDAG.getConstant(Op.getValueType().getVectorNumElements(), MVT::i32); in splitMaskArithmetic()
26 SDValue A = Op->getOperand(0); in splitMaskArithmetic()
27 SDValue B = Op->getOperand(1); in splitMaskArithmetic()
32 unsigned Opc = Op.getOpcode(); in splitMaskArithmetic()
38 SDValue VETargetLowering::lowerToVVP(SDValue Op, SelectionDAG &DAG) const { in lowerToVVP() argument
40 const unsigned Opcode = Op->getOpcode(); in lowerToVVP()
48 VECustomDAG CDAG(DAG, Op); in lowerToVVP()
53 return lowerVVP_LOAD_STORE(Op, CDAG); in lowerToVVP()
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DVECustomDAG.cpp50 bool isMaskArithmetic(SDValue Op) { in isMaskArithmetic() argument
51 switch (Op.getOpcode()) { in isMaskArithmetic()
57 return isMaskType(Op.getValueType()); in isMaskArithmetic()
85 bool maySafelyIgnoreMask(SDValue Op) { in maySafelyIgnoreMask() argument
86 auto VVPOpc = getVVPOpcode(Op->getOpcode()); in maySafelyIgnoreMask()
87 auto Opc = VVPOpc.value_or(Op->getOpcode()); in maySafelyIgnoreMask()
218 SDValue getNodeChain(SDValue Op) { in getNodeChain() argument
219 if (MemSDNode *MemN = dyn_cast<MemSDNode>(Op.getNode())) in getNodeChain()
222 switch (Op->getOpcode()) { in getNodeChain()
225 return Op->getOperand(0); in getNodeChain()
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DVEISelLowering.h129 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
140 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
141 SDValue lowerATOMIC_SWAP(SDValue Op, SelectionDAG &DAG) const;
142 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
143 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
144 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
145 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
146 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
147 SDValue lowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
148 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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/openbsd/src/gnu/llvm/llvm/tools/llvm-reduce/deltas/
DReduceOperands.cpp28 for (auto &Op : Phi->incoming_values()) { in extractOperandsFromModule() local
30 if (Value *Reduced = ReduceValue(Op)) in extractOperandsFromModule()
31 Phi->setIncomingValueForBlock(Phi->getIncomingBlock(Op), Reduced); in extractOperandsFromModule()
38 for (auto &Op : I.operands()) { in extractOperandsFromModule() local
39 if (Value *Reduced = ReduceValue(Op)) { in extractOperandsFromModule()
41 Op.set(Reduced); in extractOperandsFromModule()
48 static bool isOne(Use &Op) { in isOne() argument
49 auto *C = dyn_cast<Constant>(Op); in isOne()
53 static bool isZero(Use &Op) { in isZero() argument
54 auto *C = dyn_cast<Constant>(Op); in isZero()
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/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DMachineOperand.h264 static void printTargetFlags(raw_ostream& OS, const MachineOperand &Op);
813 MachineOperand Op(MachineOperand::MO_Immediate); in CreateImm()
814 Op.setImm(Val); in CreateImm()
815 return Op; in CreateImm()
819 MachineOperand Op(MachineOperand::MO_CImmediate); in CreateCImm()
820 Op.Contents.CI = CI; in CreateCImm()
821 return Op; in CreateCImm()
825 MachineOperand Op(MachineOperand::MO_FPImmediate); in CreateFPImm()
826 Op.Contents.CFP = CFP; in CreateFPImm()
827 return Op; in CreateFPImm()
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DMachineRegisterInfo.h857 auto UpdateOp = [this, &NewReg, &OldReg](MachineOperand &Op) { in updateDbgUsersToReg()
858 if (Op.isReg() && in updateDbgUsersToReg()
859 getTargetRegisterInfo()->regsOverlap(Op.getReg(), OldReg)) in updateDbgUsersToReg()
860 Op.setReg(NewReg); in updateDbgUsersToReg()
867 for (auto &Op : MI->debug_operands()) in updateDbgUsersToReg()
868 UpdateOp(Op); in updateDbgUsersToReg()
1040 MachineOperand *Op = nullptr;
1042 explicit defusechain_iterator(MachineOperand *op) : Op(op) { in defusechain_iterator()
1054 assert(Op && "Cannot increment end iterator!"); in advance()
1055 Op = getNextOperandForReg(Op); in advance()
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/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp402 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const { in lowerSELECT() argument
404 return MipsTargetLowering::LowerOperation(Op, DAG); in lowerSELECT()
406 EVT ResTy = Op->getValueType(0); in lowerSELECT()
407 SDLoc DL(Op); in lowerSELECT()
412 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
413 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
414 Op->getOperand(2)); in lowerSELECT()
442 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, in LowerOperation() argument
444 switch(Op.getOpcode()) { in LowerOperation()
445 case ISD::LOAD: return lowerLOAD(Op, DAG); in LowerOperation()
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/openbsd/src/gnu/llvm/llvm/tools/llvm-exegesis/lib/
DMCInstrDescView.cpp149 for (auto &Op : Operands) in create() local
150 if (Op.isExplicit() && !Op.isTied()) { in create()
153 Op.VariableIndex = VariableIndex; in create()
158 for (auto &Op : Operands) in create() local
159 if (Op.isExplicit() && Op.isTied()) in create()
160 Op.VariableIndex = Operands[Op.getTiedToIndex()].getVariableIndex(); in create()
162 for (auto &Op : Operands) in create() local
163 if (Op.isVariable()) in create()
164 Variables[Op.getVariableIndex()].TiedOperands.push_back(Op.getIndex()); in create()
170 for (const auto &Op : Operands) { in create() local
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DParallelSnippetGenerator.cpp150 const Operand &Op, const ArrayRef<InstructionTemplate> Instructions, in generateSingleRegisterForInstrAvoidingDefUseOverlap() argument
153 assert(Op.isReg() && Op.isExplicit() && !Op.isMemory() && in generateSingleRegisterForInstrAvoidingDefUseOverlap()
154 !IT.getValueFor(Op).isValid()); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
155 assert((!Op.isUse() || !Op.isTied()) && in generateSingleRegisterForInstrAvoidingDefUseOverlap()
158 if (Op.isUse()) { in generateSingleRegisterForInstrAvoidingDefUseOverlap()
165 return Instructions.front().getValueFor(Op); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
168 BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
178 BitVector PossibleRegisters = Op.getRegisterAliasing().sourceBits(); in generateSingleRegisterForInstrAvoidingDefUseOverlap()
181 if (Op.isDef()) { in generateSingleRegisterForInstrAvoidingDefUseOverlap()
187 if (Op.isUse()) { in generateSingleRegisterForInstrAvoidingDefUseOverlap()
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DSnippetGenerator.cpp59 for (const auto &Op : Variant.getInstr().Operands) { in generateConfigurations() local
60 if (Op.isDef() && Op.isImplicitReg() && in generateConfigurations()
61 ScratchRegAliases.test(Op.getImplicitReg())) in generateConfigurations()
112 const auto GetOpReg = [&IT](const Operand &Op) -> unsigned { in computeRegisterInitialValues() argument
113 if (Op.isMemory()) in computeRegisterInitialValues()
115 if (Op.isImplicitReg()) in computeRegisterInitialValues()
116 return Op.getImplicitReg(); in computeRegisterInitialValues()
117 if (Op.isExplicit() && IT.getValueFor(Op).isReg()) in computeRegisterInitialValues()
118 return IT.getValueFor(Op).getReg(); in computeRegisterInitialValues()
122 for (const Operand &Op : IT.getInstr().Operands) { in computeRegisterInitialValues() local
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/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h172 bool isTargetCanonicalConstantNode(SDValue Op) const override;
176 LegalizeAction getCustomOperationAction(SDNode &Op) const override;
178 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
186 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
187 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
188 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
189 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
190 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
191 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
192 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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/openbsd/src/gnu/llvm/llvm/include/llvm/MC/
DMCInst.h135 MCOperand Op; in createReg() local
136 Op.Kind = kRegister; in createReg()
137 Op.RegVal = Reg; in createReg()
138 return Op; in createReg()
142 MCOperand Op; in createImm() local
143 Op.Kind = kImmediate; in createImm()
144 Op.ImmVal = Val; in createImm()
145 return Op; in createImm()
149 MCOperand Op; in createSFPImm() local
150 Op.Kind = kSFPImmediate; in createSFPImm()
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/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64ISelLowering.h526 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
539 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
558 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
586 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
648 EVT getOptimalMemOpType(const MemOp &Op,
651 LLT getOptimalMemOpLLT(const MemOp &Op,
822 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
952 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
953 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
954 SDValue LowerStore128(SDValue Op, SelectionDAG &DAG) const;
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/openbsd/src/gnu/llvm/llvm/lib/Target/BPF/MCTargetDesc/
DBPFInstPrinter.cpp56 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
57 if (Op.isReg()) { in printOperand()
58 O << getRegisterName(Op.getReg()); in printOperand()
59 } else if (Op.isImm()) { in printOperand()
60 O << formatImm((int32_t)Op.getImm()); in printOperand()
62 assert(Op.isExpr() && "Expected an expression"); in printOperand()
63 printExpr(Op.getExpr(), O); in printOperand()
90 const MCOperand &Op = MI->getOperand(OpNo); in printImm64Operand() local
91 if (Op.isImm()) in printImm64Operand()
92 O << formatImm(Op.getImm()); in printImm64Operand()
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/openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/
DRISCVISelLowering.h418 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
424 bool targetShrinkDemandedConstant(SDValue Op, const APInt &DemandedBits,
428 void computeKnownBitsForTargetNode(const SDValue Op,
433 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
451 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
604 bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
651 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
652 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
653 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
654 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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/openbsd/src/gnu/llvm/clang/lib/CodeGen/
DCGExprComplex.cpp176 ComplexPairTy EmitCast(CastKind CK, Expr *Op, QualType DestTy);
270 ComplexPairTy EmitBinAdd(const BinOpInfo &Op);
271 ComplexPairTy EmitBinSub(const BinOpInfo &Op);
272 ComplexPairTy EmitBinMul(const BinOpInfo &Op);
273 ComplexPairTy EmitBinDiv(const BinOpInfo &Op);
276 const BinOpInfo &Op);
475 ComplexPairTy ComplexExprEmitter::EmitCast(CastKind CK, Expr *Op, in EmitCast() argument
487 return Visit(Op); in EmitCast()
490 LValue origLV = CGF.EmitLValue(Op); in EmitCast()
493 return EmitLoadOfLValue(CGF.MakeAddrLValue(V, DestTy), Op->getExprLoc()); in EmitCast()
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/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DLegalizeTypes.cpp312 const auto &Op = N->getOperand(i); in run() local
313 LLVM_DEBUG(dbgs() << "Analyzing operand: "; Op.dump(&DAG)); in run()
314 EVT OpVT = Op.getValueType(); in run()
521 SDValue Op = OrigOp; in AnalyzeNewNode() local
523 AnalyzeNewValue(Op); // Op may morph. in AnalyzeNewNode()
525 if (Op.getNode()->getNodeId() == Processed) in AnalyzeNewNode()
530 NewOps.push_back(Op); in AnalyzeNewNode()
531 } else if (Op != OrigOp) { in AnalyzeNewNode()
534 NewOps.push_back(Op); in AnalyzeNewNode()
710 void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) { in SetPromotedInteger() argument
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/openbsd/src/gnu/llvm/llvm/lib/Target/XCore/
DXCoreISelLowering.h104 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
165 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
166 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
167 SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
168 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
169 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
170 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
171 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
172 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
173 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DR600ISelLowering.h35 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
81 SDValue lowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
82 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
83 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
84 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
86 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
90 SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
91 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
93 SDValue lowerPrivateExtLoad(SDValue Op, SelectionDAG &DAG) const;
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DAMDGPUISelLowering.h35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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DSIISelLowering.h69 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
73 SDValue lowerImage(SDValue Op, const AMDGPU::ImageDimIntrinsicInfo *Intr,
78 SDValue lowerRawBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
80 SDValue lowerStructBufferAtomicIntrin(SDValue Op, SelectionDAG &DAG,
83 SDValue lowerWorkitemID(SelectionDAG &DAG, SDValue Op, unsigned Dim,
86 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
87 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
90 SDValue makeV_ILLEGAL(SDValue Op, SelectionDAG &DAG) const;
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/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600InstPrinter.cpp96 const MCOperand &Op = MI->getOperand(OpNo); in printLiteral() local
97 assert(Op.isImm() || Op.isExpr()); in printLiteral()
98 if (Op.isImm()) { in printLiteral()
99 int64_t Imm = Op.getImm(); in printLiteral()
102 if (Op.isExpr()) { in printLiteral()
103 Op.getExpr()->print(O << '@', &MAI); in printLiteral()
143 const MCOperand &Op = MI->getOperand(OpNo); in printOperand() local
144 if (Op.isReg()) { in printOperand()
145 switch (Op.getReg()) { in printOperand()
151 O << getRegisterName(Op.getReg()); in printOperand()
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/openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/
DWebAssemblyISelLowering.h85 void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
117 shouldSimplifyDemandedVectorElts(SDValue Op,
121 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
122 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
123 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
124 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
125 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
126 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
127 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
128 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
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/openbsd/src/gnu/llvm/llvm/lib/Target/VE/AsmParser/
DVEAsmParser.cpp67 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
592 auto Op = std::make_unique<VEOperand>(k_Token); in CreateToken() local
593 Op->Tok.Data = Str.data(); in CreateToken()
594 Op->Tok.Length = Str.size(); in CreateToken()
595 Op->StartLoc = S; in CreateToken()
596 Op->EndLoc = S; in CreateToken()
597 return Op; in CreateToken()
602 auto Op = std::make_unique<VEOperand>(k_Register); in CreateReg() local
603 Op->Reg.RegNum = RegNum; in CreateReg()
604 Op->StartLoc = S; in CreateReg()
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