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Searched refs:OSSSYS_HWIP (Results 1 – 13 of 13) sorted by relevance

/openbsd/src/sys/dev/pci/drm/amd/amdgpu/
Dvega20_ih.c322 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 2, 1)) && in vega20_ih_irq_init()
335 if ((amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0)) || in vega20_ih_irq_init()
336 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2)) || in vega20_ih_irq_init()
337 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5))) { in vega20_ih_irq_init()
367 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 0) || in vega20_ih_irq_init()
368 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2) || in vega20_ih_irq_init()
369 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 5)) in vega20_ih_irq_init()
577 (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) == IP_VERSION(4, 4, 2))) in vega20_ih_sw_init()
594 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 2) && in vega20_ih_sw_init()
595 amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(4, 4, 5)) { in vega20_ih_sw_init()
Ddimgrey_cavefish_reg_init.c45 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
Daldebaran_reg_init.c42 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in aldebaran_reg_base_init()
Darct_reg_init.c43 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in arct_reg_base_init()
Damdgpu_discovery.c221 [OSSSYS_HWIP] = OSSSYS_HWID,
1913 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { in amdgpu_discovery_set_ih_ip_blocks()
1950 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); in amdgpu_discovery_set_ih_ip_blocks()
2455 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); in amdgpu_discovery_set_ip_blocks()
2477 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); in amdgpu_discovery_set_ip_blocks()
2501 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); in amdgpu_discovery_set_ip_blocks()
2517 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); in amdgpu_discovery_set_ip_blocks()
2538 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); in amdgpu_discovery_set_ip_blocks()
2562 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); in amdgpu_discovery_set_ip_blocks()
2590 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); in amdgpu_discovery_set_ip_blocks()
Dvega10_reg_init.c46 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in vega10_reg_base_init()
Dvega20_reg_init.c45 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i])); in vega20_reg_base_init()
Dumsch_mm_v4_0.c300 memcpy(set_hw_resources.osssys_base, adev->reg_offset[OSSSYS_HWIP][0], in umsch_mm_v4_0_set_hw_resources()
303 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
Dnavi10_ih.c110 if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) < IP_VERSION(5, 0, 3)) in force_update_wptr_for_self_int()
333 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { in navi10_ih_irq_init()
Damdgpu_dev_coredump.c60 [OSSSYS_HWIP] = "OSSSYS",
Damdgpu.h722 OSSSYS_HWIP, enumerator
Dmes_v12_0.c605 adev->reg_offset[OSSSYS_HWIP][0][i]; in mes_v12_0_set_hw_resources()
Dmes_v11_0.c671 adev->reg_offset[OSSSYS_HWIP][0][i]; in mes_v11_0_set_hw_resources()