Home
last modified time | relevance | path

Searched refs:NeedAlign (Results 1 – 7 of 7) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DRegisterScavenging.cpp460 Align NeedAlign = TRI->getSpillAlign(RC); in spill() local
473 if (NeedSize > S || NeedAlign > A) in spill()
481 unsigned D = (S - NeedSize) + (A.value() - NeedAlign.value()); in spill()
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonFrameLowering.cpp1903 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2() local
1909 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1920 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1950 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2() local
1955 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1963 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1989 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec() local
1991 unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec()
2017 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec() local
2019 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec()
DHexagonISelLowering.cpp1939 HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, in validateConstPtrAlignment() argument
1946 Addr != 0 ? Align(1ull << countTrailingZeros(Addr)) : NeedAlign; in validateConstPtrAlignment()
1947 if (HaveAlign >= NeedAlign) in validateConstPtrAlignment()
1968 << ", but the memory access requires " << NeedAlign.value(); in validateConstPtrAlignment()
3138 Align NeedAlign = Subtarget.getTypeAlignment(StoreTy); in LowerStore() local
3139 if (ClaimAlign < NeedAlign) in LowerStore()
3149 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy).value(); in LowerUnalignedLoad() local
3151 if (HaveAlign >= NeedAlign) in LowerUnalignedLoad()
3171 if (!DoDefault && (2 * HaveAlign) == NeedAlign) { in LowerUnalignedLoad()
3188 assert(LoadTy.getSizeInBits() == 8*NeedAlign); in LowerUnalignedLoad()
[all …]
DHexagonInstrInfo.cpp1073 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) { in expandPostRAPseudo() argument
1076 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) { in expandPostRAPseudo()
1077 return MMO->getAlign() >= NeedAlign; in expandPostRAPseudo()
1174 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1175 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1190 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1191 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1212 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1213 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo()
1229 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
[all …]
DHexagonVectorCombine.cpp182 NeedAlign(HVC.getTypeAlignment(ValTy)) {} in AddrInfo()
190 Align NeedAlign; member
300 OS << "NeedAlign: " << AI.NeedAlign.value() << '\n'; in operator <<()
1096 getMaxOf(MoveInfos, [](const AddrInfo &AI) { return AI.NeedAlign; }); in realignGroup()
1097 Align MinNeeded = WithMaxNeeded.NeedAlign; in realignGroup()
DHexagonISelLowering.h368 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,
/openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1573 bool NeedAlign; // Does argument declaration specify alignment? in LowerCall() local
1583 NeedAlign = IsByVal || Ty->isAggregateType() || Ty->isVectorTy() || in LowerCall()
1594 NeedAlign = true; in LowerCall()
1609 NeedAlign = false; in LowerCall()
1626 if (NeedAlign) in LowerCall()