Home
last modified time | relevance | path

Searched refs:MIB (Results 1 – 25 of 182) sorted by relevance

12345678

/openbsd/src/share/snmp/
DMakefile4 FILES= OPENBSD-SNMPD-CONF.txt OPENBSD-BASE-MIB.txt
5 FILES+= OPENBSD-MEM-MIB.txt OPENBSD-SENSORS-MIB.txt
6 FILES+= OPENBSD-CARP-MIB.txt OPENBSD-PF-MIB.txt
7 FILES+= OPENBSD-RELAYD-MIB.txt
10 FILES+= BRIDGE-MIB.txt HOST-RESOURCES-MIB.txt IANA-RTPROTO-MIB.txt
11 FILES+= IANA-STORAGE-MEDIA-TYPE-MIB.txt IANAifType-MIB.txt IF-MIB.txt
12 FILES+= INET-ADDRESS-MIB.txt IP-FORWARD-MIB.txt IP-MIB.txt
13 FILES+= SNMP-FRAMEWORK-MIB.txt SNMP-USER-BASED-SM-MIB.txt SNMP-USM-AES-MIB.txt
14 FILES+= SNMP-USM-HMAC-SHA2-MIB.txt SNMPv2-CONF.txt SNMPv2-MIB.txt SNMPv2-SMI.txt
15 FILES+= SNMPv2-TC.txt SNMPv2-TM.txt TRANSPORT-ADDRESS-MIB.txt UUID-TC-MIB.txt
[all …]
DOPENBSD-SNMPD-CONF.txt21 -- present. Non-OpenBSD MIB files are not included in this distribution.
25 -- Management Information Base (MIB) for the Simple Network
28 FROM SNMPv2-MIB
30 -- IANA ifTypes MIB, http://www.iana.org/assignments/ianaiftype-mib
32 FROM IANAifType-MIB
34 -- The Interface Group MIB, RFC 2863, June 2000
36 FROM IF-MIB
41 FROM BRIDGE-MIB
46 FROM INET-ADDRESS-MIB
51 FROM IP-MIB
[all …]
DOPENBSD-MEM-MIB.txt1 -- $OpenBSD: OPENBSD-MEM-MIB.txt,v 1.3 2016/09/02 12:17:33 tb Exp $
17 OPENBSD-MEM-MIB DEFINITIONS ::= BEGIN
25 FROM IF-MIB
27 FROM OPENBSD-BASE-MIB
39 "The MIB module exporting OpenBSD memory statistics."
45 "Add the OPENBSD-MEM-MIB to snmpd."
49 -- Core MIB elements
56 -- MIB details
64 "The current version of this MIB supported by the agent.
65 The memory MIB might be updated frequently to export
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DMVETailPredUtils.h108 MachineInstrBuilder MIB = variable
110 MIB.add(MI->getOperand(1));
111 MIB.addImm(0);
112 MIB.addImm(ARMCC::AL);
113 MIB.addReg(ARM::NoRegister);
115 MachineInstrBuilder MIB = variable
117 MIB.add(MI->getOperand(0));
118 MIB.add(MI->getOperand(1));
119 MIB.addImm(0);
120 MIB.addImm(ARMCC::AL);
[all …]
DARMInstructionSelector.cpp47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
231 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
240 Register VReg0 = MIB.getReg(0); in selectMergeValues()
245 Register VReg1 = MIB.getReg(1); in selectMergeValues()
250 Register VReg2 = MIB.getReg(2); in selectMergeValues()
256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
257 MIB.add(predOps(ARMCC::AL)); in selectMergeValues()
[all …]
DARMExpandPseudoInsts.cpp577 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
605 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
609 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
611 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
613 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
615 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
619 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
622 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
623 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
650 MIB.add(AM6Offset); in ExpandVLD()
[all …]
DThumb2SizeReduction.cpp478 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1)) in ReduceLoadStore() local
486 MIB.setMemRefs(MI->memoperands()); in ReduceLoadStore()
489 MIB.setMIFlags(MI->getFlags()); in ReduceLoadStore()
590 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); in ReduceLoadStore() local
595 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead); in ReduceLoadStore()
598 MIB.add(MI->getOperand(0)); in ReduceLoadStore()
599 MIB.add(MI->getOperand(1)); in ReduceLoadStore()
602 MIB.addImm(OffsetImm / Scale); in ReduceLoadStore()
607 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) | in ReduceLoadStore()
613 MIB.add(MO); in ReduceLoadStore()
[all …]
DARMCallLowering.cpp91 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) in ARMOutgoingValueHandler()
92 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in ARMOutgoingValueHandler()
122 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
175 MachineInstrBuilder MIB; member
425 MachineInstrBuilder MIB) in CallReturnHandler()
426 : ARMIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
429 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
432 MachineInstrBuilder MIB; member
474 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode); in lowerCall() local
478 MIB.add(predOps(ARMCC::AL)); in lowerCall()
[all …]
DThumbRegisterInfo.cpp171 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg() local
173 MIB = MIB.add(t1CondCodeOp()); in emitThumbRegPlusImmInReg()
175 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill); in emitThumbRegPlusImmInReg()
177 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmInReg()
178 MIB.add(predOps(ARMCC::AL)); in emitThumbRegPlusImmInReg()
311 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg); in emitThumbRegPlusImmediate() local
313 MIB = MIB.add(t1CondCodeOp()); in emitThumbRegPlusImmediate()
314 MIB.addReg(BaseReg, RegState::Kill); in emitThumbRegPlusImmediate()
316 MIB.addImm(CopyImm); in emitThumbRegPlusImmediate()
318 MIB.setMIFlags(MIFlags).add(predOps(ARMCC::AL)); in emitThumbRegPlusImmediate()
[all …]
DARMBlockPlacement.cpp123 MachineInstrBuilder MIB = in revertWhileToDoLoop() local
128 MIB.add(WLS->getOperand(0)); in revertWhileToDoLoop()
129 MIB.add(WLS->getOperand(1)); in revertWhileToDoLoop()
131 MIB.add(WLS->getOperand(2)); in revertWhileToDoLoop()
277 MachineInstrBuilder MIB = in moveBasicBlock() local
279 MIB.addMBB(To); in moveBasicBlock()
280 MIB.addImm(ARMCC::CondCodes::AL); in moveBasicBlock()
281 MIB.addReg(ARM::NoRegister); in moveBasicBlock()
284 << *MIB.getInstr()); in moveBasicBlock()
/openbsd/src/gnu/llvm/llvm/lib/Target/X86/
DX86InstrBuilder.h124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
143 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
157 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
[all …]
DX86FixupBWInsts.cpp300 MachineInstrBuilder MIB = in tryReplaceLoad() local
305 MIB.add(MI->getOperand(i)); in tryReplaceLoad()
307 MIB.setMemRefs(MI->memoperands()); in tryReplaceLoad()
311 unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(), in tryReplaceLoad()
313 unsigned NewInstrNum = MIB->getDebugInstrNum(*MF); in tryReplaceLoad()
317 return MIB; in tryReplaceLoad()
343 MachineInstrBuilder MIB = in tryReplaceCopy() local
351 MIB.add(Op); in tryReplaceCopy()
353 return MIB; in tryReplaceCopy()
371 MachineInstrBuilder MIB = in tryReplaceExtend() local
[all …]
DX86CallLowering.cpp87 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) in X86OutgoingValueHandler()
88 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), in X86OutgoingValueHandler()
110 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
126 MachineInstrBuilder &MIB; member
148 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn() local
167 X86OutgoingValueHandler Handler(MIRBuilder, MRI, MIB); in lowerReturn()
174 MIRBuilder.insertInstr(MIB); in lowerReturn()
239 MachineInstrBuilder &MIB) in CallReturnHandler()
240 : X86IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
243 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp599 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
603 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
604 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
744 auto MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_AND_B32_e32), TmpReg) in selectG_BUILD_VECTOR() local
747 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
750 MIB = BuildMI(*BB, MI, DL, TII.get(AMDGPU::V_LSHL_OR_B32_e64), Dst) in selectG_BUILD_VECTOR()
754 if (!constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI)) in selectG_BUILD_VECTOR()
795 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR() local
800 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR()
906 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(Opc), DstReg) in selectG_SBFX_UBFX() local
[all …]
DAMDGPUCallLowering.cpp47 MachineInstrBuilder MIB) in AMDGPUOutgoingValueHandler()
48 : OutgoingValueHandler(B, MRI), MIB(MIB) {} in AMDGPUOutgoingValueHandler()
50 MachineInstrBuilder MIB; member
92 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
165 MachineInstrBuilder MIB) in CallReturnHandler()
166 : AMDGPUIncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
169 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
172 MachineInstrBuilder MIB; member
186 MachineRegisterInfo &MRI, MachineInstrBuilder MIB, in AMDGPUOutgoingArgHandler()
188 : AMDGPUOutgoingValueHandler(MIRBuilder, MRI, MIB), FPDiff(FPDiff), in AMDGPUOutgoingArgHandler()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp187 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
225 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
238 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
250 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
293 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
305 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
354 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
356 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
357 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
364 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
DCSEMIRBuilder.cpp123 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB, in memoizeMI() argument
125 assert(canPerformCSEForOpc(MIB->getOpcode()) && in memoizeMI()
127 MachineInstr *MIBInstr = MIB; in memoizeMI()
129 return MIB; in memoizeMI()
144 MachineInstrBuilder &MIB) { in generateCopiesIfRequired() argument
150 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
160 Observer->changingInstr(*MIB); in generateCopiesIfRequired()
161 MIB->setDebugLoc( in generateCopiesIfRequired()
162 DILocation::getMergedLocation(MIB->getDebugLoc(), getDebugLoc())); in generateCopiesIfRequired()
164 Observer->changedInstr(*MIB); in generateCopiesIfRequired()
[all …]
DMachineIRBuilder.cpp43 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { in insertInstr() argument
44 getMBB().insert(getInsertPt(), MIB); in insertInstr()
45 recordInsertion(MIB); in insertInstr()
46 return MIB; in insertInstr()
98 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); in buildConstDbgValue() local
109 MIB.addCImm(CI); in buildConstDbgValue()
111 MIB.addImm(CI->getZExtValue()); in buildConstDbgValue()
113 MIB.addFPImm(CFP); in buildConstDbgValue()
115 MIB.addImm(0); in buildConstDbgValue()
118 MIB.addReg(Register()); in buildConstDbgValue()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp82 MIB.setMF(MF); in setupMF()
124 MachineIRBuilder &MIB) const;
126 MachineIRBuilder &MIB) const;
128 MachineIRBuilder &MIB) const;
131 MachineIRBuilder &MIB) const;
303 MachineIRBuilder &MIB) const;
308 MachineIRBuilder &MIB) const;
312 MachineIRBuilder &MIB) const;
319 MachineIRBuilder &MIB) const;
324 MachineIRBuilder &MIB) const;
[all …]
DAArch64CallLowering.cpp217 MachineInstrBuilder MIB) in CallReturnHandler()
218 : IncomingArgHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
221 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
224 MachineInstrBuilder MIB; member
231 MachineInstrBuilder MIB) in ReturnedArgCallReturnHandler()
232 : CallReturnHandler(MIRBuilder, MRI, MIB) {} in ReturnedArgCallReturnHandler()
239 MachineInstrBuilder MIB, bool IsTailCall = false, in OutgoingArgHandler()
241 : OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB), IsTailCall(IsTailCall), in OutgoingArgHandler()
286 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
327 MachineInstrBuilder MIB; member
[all …]
DAArch64PostLegalizerLowering.cpp547 MachineIRBuilder MIB(MI); in applyVAshrLshrImm() local
548 auto ImmDef = MIB.buildConstant(LLT::scalar(32), Imm); in applyVAshrLshrImm()
549 MIB.buildInstr(NewOpc, {MI.getOperand(0)}, {MI.getOperand(1), ImmDef}); in applyVAshrLshrImm()
673 MachineIRBuilder &MIB, GISelChangeObserver &Observer) { in applyAdjustICmpImmAndPred() argument
674 MIB.setInstrAndDebugLoc(MI); in applyAdjustICmpImmAndPred()
676 MachineRegisterInfo &MRI = *MIB.getMRI(); in applyAdjustICmpImmAndPred()
677 auto Cst = MIB.buildConstant(MRI.cloneVirtualRegister(RHS.getReg()), in applyAdjustICmpImmAndPred()
908 return [LHS, RHS, IsZero, DstTy](MachineIRBuilder &MIB) { in getVectorFCMP() argument
910 ? MIB.buildInstr(AArch64::G_FCMEQZ, {DstTy}, {LHS}) in getVectorFCMP()
911 : MIB.buildInstr(AArch64::G_FCMEQ, {DstTy}, {LHS, RHS}); in getVectorFCMP()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp568 MachineInstrBuilder MIB; in changeLoad() local
574 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
575 MIB.add(OldMI->getOperand(0)); in changeLoad()
576 MIB.add(OldMI->getOperand(2)); in changeLoad()
577 MIB.add(OldMI->getOperand(3)); in changeLoad()
578 MIB.add(ImmOp); in changeLoad()
585 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
590 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
597 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); in changeLoad()
602 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
[all …]
/openbsd/src/gnu/llvm/llvm/lib/Analysis/
DMemoryProfileInfo.cpp55 MDNode *llvm::memprof::getMIBStackNode(const MDNode *MIB) { in getMIBStackNode() argument
56 assert(MIB->getNumOperands() == 2); in getMIBStackNode()
58 return cast<MDNode>(MIB->getOperand(0)); in getMIBStackNode()
61 AllocationType llvm::memprof::getMIBAllocType(const MDNode *MIB) { in getMIBAllocType() argument
62 assert(MIB->getNumOperands() == 2); in getMIBAllocType()
66 auto *MDS = dyn_cast<MDString>(MIB->getOperand(1)); in getMIBAllocType()
133 void CallStackTrie::addCallStack(MDNode *MIB) { in addCallStack() argument
134 MDNode *StackMD = getMIBStackNode(MIB); in addCallStack()
143 addCallStack(getMIBAllocType(MIB), CallStack); in addCallStack()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMicroMipsSizeReduction.cpp711 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); in ReplaceInstruction() local
714 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
717 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
718 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
723 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
724 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
725 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
727 MIB.add(MI->getOperand(0)); in ReplaceInstruction()
728 MIB.add(MI->getOperand(2)); in ReplaceInstruction()
729 MIB.add(MI->getOperand(1)); in ReplaceInstruction()
[all …]
DMipsCallLowering.cpp117 MachineInstrBuilder &MIB) in CallReturnHandler() argument
118 : MipsIncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {} in CallReturnHandler()
122 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
125 MachineInstrBuilder &MIB; member in __anon67a341860111::CallReturnHandler
197 MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) in MipsOutgoingValueHandler() argument
199 STI(MIRBuilder.getMF().getSubtarget<MipsSubtarget>()), MIB(MIB) {} in MipsOutgoingValueHandler()
215 MachineInstrBuilder &MIB; member in __anon67a341860211::MipsOutgoingValueHandler
224 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
477 MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert( in lowerCall() local
479 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
[all …]

12345678