Home
last modified time | relevance | path

Searched refs:MI0 (Results 1 – 9 of 9) sorted by relevance

/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64CollectLOH.cpp284 const MachineInstr *MI0; ///< First instruction involved in the LOH. member
305 Info.MI0 = &MI; in handleUse()
311 Info.MI0 = &MI; in handleUse()
316 Info.MI0 = &MI; in handleUse()
322 Info.MI0 = &MI; in handleUse()
402 const MachineInstr *AddMI = Info.MI0; in handleADRP()
409 << '\t' << MI << '\t' << *Info.MI0); in handleADRP()
410 AFI.addLOHDirective(MCLOH_AdrpAdd, {&MI, Info.MI0}); in handleADRP()
415 if (supportLoadFromLiteral(*Info.MI0)) { in handleADRP()
417 << '\t' << MI << '\t' << *Info.MI0); in handleADRP()
[all …]
DAArch64MachineScheduler.cpp36 static bool mayOverlapWrite(const MachineInstr &MI0, const MachineInstr &MI1, in mayOverlapWrite() argument
38 const MachineOperand &Base0 = AArch64InstrInfo::getLdStBaseOp(MI0); in mayOverlapWrite()
45 int StoreSize0 = AArch64InstrInfo::getMemScale(MI0); in mayOverlapWrite()
47 Off0 = AArch64InstrInfo::hasUnscaledLdStOffset(MI0.getOpcode()) in mayOverlapWrite()
48 ? AArch64InstrInfo::getLdStOffsetOp(MI0).getImm() in mayOverlapWrite()
49 : AArch64InstrInfo::getLdStOffsetOp(MI0).getImm() * StoreSize0; in mayOverlapWrite()
54 const MachineInstr &MI = (Off0 < Off1) ? MI0 : MI1; in mayOverlapWrite()
/openbsd/src/gnu/llvm/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp1475 auto MI0 = in expandLSLW4Rd() local
1481 MI0->getOperand(3).setIsDead(); in expandLSLW4Rd()
1561 auto MI0 = in expandLSLW12Rd() local
1567 MI0->getOperand(3).setIsDead(); in expandLSLW12Rd()
1673 auto MI0 = in expandLSRW4Rd() local
1679 MI0->getOperand(3).setIsDead(); in expandLSRW4Rd()
1759 auto MI0 = in expandLSRW12Rd() local
1765 MI0->getOperand(3).setIsDead(); in expandLSRW12Rd()
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp1860 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0, in produceSameValue() argument
1863 unsigned Opcode = MI0.getOpcode(); in produceSameValue()
1872 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1875 const MachineOperand &MO0 = MI0.getOperand(1); in produceSameValue()
1887 const MachineFunction *MF = MI0.getParent()->getParent(); in produceSameValue()
1908 if (MI0.getNumOperands() != MI1.getNumOperands()) in produceSameValue()
1911 Register Addr0 = MI0.getOperand(1).getReg(); in produceSameValue()
1926 for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) { in produceSameValue()
1928 const MachineOperand &MO0 = MI0.getOperand(i); in produceSameValue()
1936 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
DARMBaseInstrInfo.h239 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/
DTargetInstrInfo.cpp426 bool TargetInstrInfo::produceSameValue(const MachineInstr &MI0, in produceSameValue() argument
429 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs); in produceSameValue()
/openbsd/src/gnu/llvm/llvm/include/llvm/CodeGen/
DTargetInstrInfo.h586 virtual bool produceSameValue(const MachineInstr &MI0,
/openbsd/src/gnu/usr.bin/binutils/gdb/testsuite/gdb.mi/
DChangeLog-1999-2003299 MI0 was the never enabled MI interface included in GDB 5.0.
/openbsd/src/gnu/llvm/llvm/lib/CodeGen/GlobalISel/
DCombinerHelper.cpp5305 static bool hasMoreUses(const MachineInstr &MI0, const MachineInstr &MI1, in hasMoreUses() argument
5307 return std::distance(MRI.use_instr_nodbg_begin(MI0.getOperand(0).getReg()), in hasMoreUses()