Searched refs:MFOCRF (Results 1 – 11 of 11) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCBack2BackFusion.def | 109 MFOCRF,
635 MFOCRF,
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| D | PPCRegisterInfo.cpp | 974 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRSpilling()
1132 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg) in lowerCRBitSpilling()
1187 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO) in lowerCRBitRestore()
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| D | PPCISelLowering.h | 219 MFOCRF, enumerator
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| D | PPC.td | 91 "Enable the MFOCRF instruction">;
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| D | PPCAsmPrinter.cpp | 1428 case PPC::MFOCRF: in emitInstruction()
1434 MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8; in emitInstruction()
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| D | PPCISelDAGToDAG.cpp | 4464 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, in trySETCC()
5223 SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR6Reg, in Select()
5324 case PPCISD::MFOCRF: { in Select()
5326 ReplaceNode(N, CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, in Select()
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| D | P10InstrResources.td | 932 MFOCRF, MFOCRF8,
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| D | PPCInstrInfo.cpp | 1714 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg); in copyPhysReg()
1728 unsigned MvCode = Is64Bit ? PPC::MFOCRF8 : PPC::MFOCRF; in copyPhysReg()
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| D | PPCISelLowering.cpp | 1686 case PPCISD::MFOCRF: return "PPCISD::MFOCRF"; in getTargetNodeName()
10785 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32, in LowerINTRINSIC_WO_CHAIN()
15884 if (FlagUser->getOpcode() == PPCISD::MFOCRF) in PerformDAGCombine()
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| D | PPCInstrInfo.td | 2690 def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| D | PPCMCCodeEmitter.cpp | 411 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) && in get_crbitm_encoding()
438 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) || in getMachineOpValue()
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