Searched refs:MFMA (Results 1 – 8 of 8) sorted by relevance
2403 const MachineInstr *MFMA = nullptr; in checkMAIVALUHazards() local2405 auto IsMFMAWriteFn = [&Reg, &MFMA, this](const MachineInstr &MI) { in checkMAIVALUHazards()2409 MFMA = &MI; in checkMAIVALUHazards()2497 MFMA = nullptr; in checkMAIVALUHazards()2500 if (!MFMA) in checkMAIVALUHazards()2503 unsigned HazardDefLatency = TSchedModel.computeInstrLatency(MFMA); in checkMAIVALUHazards()2509 ? isXDL(ST, *MFMA) in checkMAIVALUHazards()2515 assert(isDGEMM(MFMA->getOpcode()) || ST.hasGFX940Insts()); in checkMAIVALUHazards()2517 isDGEMM(MFMA->getOpcode()) in checkMAIVALUHazards()2520 : isXDL(ST, *MFMA) in checkMAIVALUHazards()[all …]
71 MFMA = 1u << 3, enumerator78 ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |779 SchedGroupMask::MFMA, 1, PipelineSyncID, DAG, TII); in applyIGLPStrategy()862 else if (((SGMask & SchedGroupMask::MFMA) != SchedGroupMask::NONE) && in canAddMI()1070 ~SchedGroupMask::VALU & ~SchedGroupMask::SALU & ~SchedGroupMask::MFMA; in invertSchedBarrierMask()1074 (InvertedMask & SchedGroupMask::MFMA) == SchedGroupMask::NONE) in invertSchedBarrierMask()
119 def HWXDL : ProcResource<1> { // MFMA CU
134 // This bit indicates that this is one of MFMA instructions.
195 "MFMA cannot use inline literal as SrcC"
330 // MFMA builtins.
235 // MASK = 0x0000 0008: MFMA/WMMA instructions may be scheduled across SCHED_BARRIER.2321 // Note: in gfx940 BLGP argument is replaced by NEG bitfield in the DGEMM MFMA.
2003 VOP3P MFMA Modifiers