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/openbsd/src/gnu/llvm/llvm/docs/
DBigEndianNEON.rst52 ``LDR`` and ``LD1``
58 Big endian vector load using ``LDR``.
61 …In little endian mode, we can do this by just performing a 64-bit load - ``LDR q0, [foo]``. Howeve…
75 …1. The content of a vector register is the same *as if* it had been loaded with an ``LDR`` instruc…
78 Because ``LD1 == LDR + REV`` and similarly ``LDR == LD1 + REV`` (on a big endian system), we can si…
95 Use of ``LDR`` would break this lane ordering property. This doesn't preclude the use of ``LDR``, b…
97 1. Insert a ``REV`` instruction to reverse the lane order after every ``LDR``.
105 …e register; a short vector is loaded from memory using the corresponding ``LDR`` instruction. On a…
109 The use of ``LDR`` and ``STR`` as the ABI defines has at least one advantage over ``LD1`` and ``ST1…
128 So to preserve ABI compatibility, we need to use the ``LDR`` lane layout across function calls.
[all …]
/openbsd/src/gnu/llvm/compiler-rt/lib/xray/
Dxray_trampoline_AArch64.S37 LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE]
90 LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE]
139 LDR X2, [X1, #:lo12:_ZN6__xray19XRayPatchedFunctionE]
Dxray_trampoline_arm.S26 LDR r2, [pc, r1]
58 LDR r2, [pc, r1]
89 LDR r2, [pc, r1]
/openbsd/src/usr.bin/file/magdir/
Dintel43 >7 string LDR UNDI image
Dfilesystems80 >>>>>329 string Moved\ or\ missing\ IBMBIO.LDR\n\r
83 >>>>>>>>411 string Caldera\ Inc.\0 \b, DR-DOS MBR (IBMBIO.LDR)
307 # DOS names like NTLDR,CMLDR,$LDR$ are 8 right space padded bytes+3 bytes
/openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/
DAArch64SchedExynosM3.td522 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
524 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
566 def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>;
569 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
570 def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>;
572 ReadAdrBase], (instregex "^LDR[BDHS]roW")>;
574 ReadAdrBase], (instregex "^LDR[BDHS]roX")>;
DAArch64SchedTSV110.td440 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(W|X)l$")>;
443 def : InstRW<[TSV110Wr_4cyc_1LdSt], (instregex "^LDR(BB|HH|W|X)ui$")>;
446 def : InstRW<[TSV110Wr_4cyc_1LdSt, WriteAdr], (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
525 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[DSQ]l")>;
527 def : InstRW<[TSV110Wr_5cyc_1LdSt, WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>;
528 def : InstRW<[TSV110Wr_5cyc_1LdSt], (instregex "^LDR[BDHSQ]ui")>;
529 def : InstRW<[TSV110Wr_6cyc_1LdSt_1ALUAB, ReadAdrBase], (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
DAArch64SchedExynosM5.td676 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
678 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
737 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
740 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
741 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
743 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
745 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
DAArch64SchedExynosM4.td619 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>;
621 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>;
681 def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
684 WriteAdr], (instregex "^LDR[BHSDQ](post|pre)")>;
685 def : InstRW<[WriteVLD], (instregex "^LDR[BHSDQ]ui")>;
687 ReadAdrBase], (instregex "^LDR[BHSDQ]roW")>;
689 ReadAdrBase], (instregex "^LDR[BHSD]roX")>;
DAArch64SchedFalkorDetails.td1092 (instregex "^LDR((Q|D|S|H|B)ui|(Q|D|S)l)$")>;
1094 (instregex "^LDR(Q|D|S|H|B)(post|pre)$")>;
1098 (instregex "^LDR(Q|D|H|S|B)ro(W|X)$")>;
1174 (instregex "^LDR(BB|HH|W|X)ui$")>;
1176 (instregex "^LDR(BB|HH|W|X)(post|pre)$")>;
1178 (instregex "^LDR(BB|HH|W|X)ro(W|X)$")>;
1180 (instregex "^LDR(W|X)l$")>;
DAArch64SchedAmpere1.td801 def : InstRW<[Ampere1Write_6cyc_1AB_1L], (instregex "LDR[BHSDQ]ro(W|X)")>;
960 (instregex "LDR(B|D|H|Q|S)ui")>;
962 (instregex "LDR(D|Q|W|X)l")>;
972 (instregex "LDR(HH|SHW|SHX|W|X)ro(W|X)")>;
DAArch64SchedKryoDetails.td1462 (instregex "LDR((D|S)l|(D|S|H|B)ui)")>;
1474 (instregex "LDR(D|S|H|B)ro(W|X)")>;
1480 (instregex "LDR(D|S|H|B)(post|pre)")>;
1486 (instregex "LDR(BB|HH|W|X)ui")>;
1492 (instregex "LDR(BB|HH|W|X)(post|pre)")>;
1498 (instregex "(LDR(BB|HH|W|X)ro(W|X)|PRFMro(W|X))")>;
DAArch64SchedNeoverseN2.td836 def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[SDQ]l$",
840 def : InstRW<[N2Write_6cyc_1I_1L, WriteI], (instregex "^LDR[BHSDQ]post$")>;
842 def : InstRW<[N2Write_6cyc_1I_1L, WriteAdr], (instregex "^LDR[BHSDQ]pre$")>;
845 def : InstRW<[N2Write_6cyc_1L], (instregex "^LDR[BHSDQ]ui$")>;
851 def : InstRW<[N2Write_6cyc_1L, ReadAdrBase], (instregex "^LDR[BSD]ro[WX]$")>;
855 def : InstRW<[N2Write_7cyc_1I_1L, ReadAdrBase], (instregex "^LDR[HQ]ro[WX]$")>;
DAArch64SchedCyclone.td243 // EXAMPLE: LDR Xn, Xm [, lsl 3]
256 // EXAMPLE: LDR Xn, Xm [, lsl 3]
/openbsd/src/gnu/llvm/llvm/lib/Target/ARM/
DREADME.txt504 Split out LDR (literal) from normal ARM LDR instruction. Also consider spliting
505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
506 ARMLoadStoreOptimizer does not need to look at LDR (literal) and LDR (so_reg)
507 while ARMConstantIslandPass only need to worry about LDR (literal).
DARMScheduleA57.td377 // LDR and LDRB have LDRi12 and LDRBi12 forms for immediate
390 def : InstRW<[A57WriteLdrAm3], (instregex "LDR(H|SH|SB)$")>;
418 // --- LDR pre-indexed ---
437 (instregex "LDR(H|SH|SB)_PRE")>;
455 // --- LDR post-indexed ---
456 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackOne], (instregex "LDR(T?)_POST_IMM",
457 "LDRB(T?)_POST_IMM", "LDR(SB|H|SH)Ti", "t2LDRB_POST")>;
464 (instregex "LDR(H|SH|SB)_POST")>;
469 "LDRB_POST_REG", "LDR(B?)T_POST$")>;
483 def : InstRW<[A57Write_4cyc_1L_1I, A57WrBackTwo], (instregex "LDR(SB|H|SH)Tr")>;
DARMScheduleR52.td291 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
299 "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
301 "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
511 // LDRLIT pseudo instructions, they expand to LDR + PICADD
514 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
DARMScheduleSwift.td357 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
367 "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
370 (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
540 // LDRLIT pseudo instructions, they expand to LDR + PICADD
543 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
DARMScheduleM4.td56 def : M4UnitL2I<(instregex "(t|t2)LDR")>;
/openbsd/src/gnu/usr.bin/binutils/gas/doc/
Dc-arm.texi415 @cindex @code{LDR reg,=<label>} pseudo op, ARM
416 @item LDR
422 instruction will be used in place of the LDR instruction, if the
425 already there) and a PC relative LDR instruction will be generated.
/openbsd/src/gnu/usr.bin/binutils-2.17/gas/doc/
Dc-arm.texi559 @cindex @code{LDR reg,=<label>} pseudo op, ARM
560 @item LDR
566 instruction will be used in place of the LDR instruction, if the
569 already there) and a PC relative LDR instruction will be generated.
/openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/
DSystemZElimCompare.cpp119 case SystemZ::LDR: in preservesValueOf()
DSystemZInstrFP.td46 def LDR : UnaryRR <"ldr", 0x28, null_frag, FP64, FP64>;
49 // For z13 we prefer LDR over LER to avoid partial register dependencies.
DSystemZInstrInfo.cpp851 Opcode = SystemZ::LDR; in copyPhysReg()
1697 case SystemZ::LDR: return SystemZ::LTDBR; in getLoadAndTest()
/openbsd/src/gnu/llvm/llvm/lib/Target/Mips/
DMipsISelLowering.h253 LDR, enumerator

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