| /openbsd/src/lib/libc/arch/powerpc64/sys/ |
| D | brk.S | 39 addis %r5, %r2, .LC0@toc@ha
40 ld %r5, .LC0@toc@l(%r5) /* # %r5 = &_end */
74 .LC0: label
|
| /openbsd/src/gnu/usr.bin/binutils/gdb/testsuite/gdb.arch/ |
| D | gdb1291.s | 52 .LC0: label
81 .long .LC0
|
| D | gdb1431.s | 52 .LC0: label
81 .long .LC0
|
| /openbsd/src/gnu/gcc/gcc/config/bfin/ |
| D | lib1funcs.asm | 86 LSETUP (0f, 1f) LC0 = P0;
|
| /openbsd/src/regress/lib/libcrypto/x509/bettertls/certificates/ |
| D | 1907.chain | 18 eQ5DISsy0CDIojKTdQ17zNGACJDyW4wy39n2vC8IvQoRu98j6wk+ENZTODBt+LC0
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 112 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R || in isLoopRegister()
|
| D | HexagonMCChecker.cpp | 47 Defs[Hexagon::LC0].insert(Unconditional); in init()
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonPseudo.td | 91 Defs = [PC, LC0], Uses = [SA0, LC0] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
149 let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
|
| D | HexagonRegisterInfo.cpp | 163 Reserved.set(Hexagon::LC0); // C1 in getReservedRegs()
|
| D | HexagonRegisterInfo.td | 174 def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>;
206 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>;
560 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
|
| D | HexagonHardwareLoops.cpp | 1007 static const Register Regs01[] = { LC0, SA0, LC1, SA1 }; in isInvalidLoopOperation()
|
| D | HexagonISelLowering.cpp | 328 .Case("lc0", Hexagon::LC0) in getRegisterByName()
|
| D | HexagonDepInstrInfo.td | 5022 let Uses = [LC0, SA0];
5023 let Defs = [LC0, P3, PC, USR];
5033 let Uses = [LC0, LC1, SA0, SA1];
5034 let Defs = [LC0, LC1, P3, PC, USR];
5646 let Defs = [LC0, SA0, USR];
5664 let Defs = [LC0, SA0, USR];
5728 let Defs = [LC0, P3, SA0, USR];
5747 let Defs = [LC0, P3, SA0, USR];
5765 let Defs = [LC0, P3, SA0, USR];
5784 let Defs = [LC0, P3, SA0, USR];
[all …]
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | README-X86-64.txt | 14 ucomiss LC0(%rip), %xmm0
17 subss LC0(%rip), %xmm0
|
| D | README-SSE.txt | 632 movdqa LC0, %xmm0
638 LC0:
649 movdqa .LC0(%rip), %xmm0
|
| /openbsd/src/gnu/usr.bin/binutils-2.17/gas/doc/ |
| D | c-bfin.texi | 131 LC0 and LC1. These registers contain the 32-bit counter of the zero
|
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 673 /* 0 */ SA0, LC0, SA1, LC1, in DecodeCtrRegsRegisterClass()
|
| /openbsd/src/gnu/usr.bin/binutils/gdb/doc/ |
| D | stabs.texinfo | 351 22 LC0:
367 38 sethi %hi(LC0),%o1
368 39 or %o1,%lo(LC0),%o0
|
| /openbsd/src/gnu/gcc/gcc/doc/ |
| D | md.texi | 2191 LC0 or LC1.
|
| D | gcc.info | 18838 LC0 or LC1.
|
| D | gccint.info | 14119 LC0 or LC1.
|