Searched refs:IsROTL (Results 1 – 2 of 2) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 2036 bool IsROTL = (Op.getOpcode() == ISD::ROTL); in SimplifyDemandedBits() local
2048 APInt Demanded0 = DemandedBits.rotr(IsROTL ? Amt : RevAmt); in SimplifyDemandedBits()
2059 DemandedBits.countTrailingZeros() >= (IsROTL ? Amt : RevAmt)) { in SimplifyDemandedBits()
2060 Op1 = TLO.DAG.getConstant(IsROTL ? Amt : RevAmt, dl, Op1.getValueType()); in SimplifyDemandedBits()
2064 DemandedBits.countLeadingZeros() >= (IsROTL ? RevAmt : Amt)) { in SimplifyDemandedBits()
2065 Op1 = TLO.DAG.getConstant(IsROTL ? RevAmt : Amt, dl, Op1.getValueType()); in SimplifyDemandedBits()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 31161 bool IsROTL = Opcode == ISD::ROTL; in LowerRotate() local
31175 unsigned RotOpc = IsROTL ? X86ISD::VROTLI : X86ISD::VROTRI; in LowerRotate()
31187 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
31193 if (!IsROTL) { in LowerRotate()
31213 assert(IsROTL && "Only ROTL expected"); in LowerRotate()
31255 unsigned FunnelOpc = IsROTL ? ISD::FSHL : ISD::FSHR; in LowerRotate()
31258 unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI; in LowerRotate()
31265 return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL); in LowerRotate()
31276 unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL; in LowerRotate()
31293 if (IsROTL) in LowerRotate()
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