| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSERegisterInfo.cpp | 200 bool IsKill = false; in eliminateFI() local
235 IsKill = true; in eliminateFI()
252 IsKill = true; in eliminateFI()
256 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| D | Mips16RegisterInfo.cpp | 123 bool IsKill = false; in eliminateFI() local
139 IsKill = true; in eliminateFI()
141 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| D | MipsSEFrameLowering.cpp | 833 bool IsKill = !IsRAAndRetAddrIsTaken; in spillCalleeSavedRegisters() local
835 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, I.getFrameIdx(), RC, TRI, in spillCalleeSavedRegisters()
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| /openbsd/src/gnu/llvm/llvm/lib/CodeGen/ |
| D | FixupStatepointCallerSaved.cpp | 112 bool &IsKill, const TargetInstrInfo &TII, in performCopyPropagation() argument
117 IsKill = false; in performCopyPropagation()
154 IsKill = DestSrc->Source->isKill(); in performCopyPropagation()
161 } else if (IsKill) { in performCopyPropagation()
419 bool IsKill = true; in spillRegisters() local
421 Reg = performCopyPropagation(Reg, InsertBefore, IsKill, TII, TRI); in spillRegisters()
424 TII.storeRegToStackSlot(*MI.getParent(), InsertBefore, Reg, IsKill, FI, in spillRegisters()
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| D | ScheduleDAGInstrs.cpp | 400 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); in addVRegDefDeps() local
404 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask; in addVRegDefDeps()
1106 bool IsKill = LiveRegs.available(MRI, Reg); in toggleKills() local
1107 MO.setIsKill(IsKill); in toggleKills()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.cpp | 126 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
136 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
141 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 84 bool IsKill; member
120 bool IsKill, int Index, RegScavenger *RS) in SGPRSpillBuilder()
121 : SuperReg(Reg), MI(MI), IsKill(IsKill), DL(MI->getDebugLoc()), in SGPRSpillBuilder()
1193 unsigned ValueReg, bool IsKill) { in spillVGPRtoAGPR() argument
1217 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1225 .addReg(Src, getKillRegState(IsKill)); in spillVGPRtoAGPR()
1308 unsigned LoadStoreOp, int Index, Register ValueReg, bool IsKill, in buildSpillLoadStore() argument
1531 SrcDstRegState |= getKillRegState(IsKill); in buildSpillLoadStore()
1556 auto MIB = spillVGPRtoAGPR(ST, MBB, MI, Index, Lane, Sub, IsKill); in buildSpillLoadStore()
1601 .addReg(SubReg, getKillRegState(IsKill)); in buildSpillLoadStore()
[all …]
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| D | SIShrinkInstructions.cpp | 312 bool IsKill = NewAddrDwords == Info->VAddrDwords; in shrinkMIMG() local
331 IsKill = false; in shrinkMIMG()
364 MI.getOperand(VAddr0Idx).setIsKill(IsKill); in shrinkMIMG()
532 const bool IsKill = SrcReg->isKill(); in shrinkScalarLogicOp() local
539 /*isImp*/ false, IsKill, in shrinkScalarLogicOp()
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| D | SIOptimizeExecMaskingPreRA.cpp | 282 bool IsKill = SelLI->Query(CmpIdx.getRegSlot()).isKill(); in optimizeVcndVcmpPair() local
285 if (MRI->use_nodbg_empty(SelReg) && (IsKill || IsDead)) { in optimizeVcndVcmpPair()
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| D | SIRegisterInfo.h | 137 bool IsLoad, bool IsKill = true) const;
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| D | SIFrameLowering.cpp | 140 bool IsKill = !MBB.isLiveIn(SpillReg); in buildPrologSpill() local
141 TRI.buildSpillLoadStore(MBB, I, DL, Opc, FI, SpillReg, IsKill, FrameReg, in buildPrologSpill()
143 if (IsKill) in buildPrologSpill()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARC/ |
| D | ARCInstrInfo.h | 72 bool IsKill, int FrameIndex,
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| D | ARCInstrInfo.cpp | 295 bool IsKill, int FrameIndex, const TargetRegisterClass *RC, in storeRegToStackSlot() argument
314 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1416 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); in insertCSRSpillsInBlock() local
1419 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI, Register()); in insertCSRSpillsInBlock()
1420 if (IsKill) in insertCSRSpillsInBlock()
1747 bool IsKill = MI->getOperand(2).isKill(); in expandStoreInt() local
1756 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1810 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVecPred() local
1825 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1899 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec2() local
1914 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
1925 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
[all …]
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| D | HexagonBlockRanges.cpp | 326 bool IsKill = Op.isKill(); in computeInitialLiveRanges() local
329 if (IsKill) in computeInitialLiveRanges()
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| D | HexagonFrameLowering.h | 173 bool IsDef, bool IsKill) const;
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 275 unsigned Dst, unsigned Src, bool IsKill) { in insertCopy() argument
278 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
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| D | AArch64InstrInfo.cpp | 3804 Register SrcReg, bool IsKill, in storeRegPairToStackSlot() argument
3816 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
3817 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 56 Register SourceRegister, bool IsKill, int FrameIndex,
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| D | LanaiInstrInfo.cpp | 51 Register SourceRegister, bool IsKill, int FrameIndex, in storeRegToStackSlot() argument
63 .addReg(SourceRegister, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /openbsd/src/gnu/llvm/llvm/lib/Support/Unix/ |
| D | Signals.inc | 303 enum class SignalKind { IsKill, IsInfo };
312 case SignalKind::IsKill:
330 registerHandler(S, SignalKind::IsKill);
332 registerHandler(S, SignalKind::IsKill);
334 registerHandler(SIGPIPE, SignalKind::IsKill);
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.h | 63 bool IsKill, int FrameIndex,
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| D | RISCVInstrInfo.cpp | 465 Register SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
531 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
540 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /openbsd/src/gnu/llvm/llvm/lib/Transforms/Utils/ |
| D | BasicBlockUtils.cpp | 523 bool IsKill = DVI->isKillLocation() && IsDbgValueKind; in remomveUndefDbgAssignsFromEntryBlock() local
524 if (!IsKill) { in remomveUndefDbgAssignsFromEntryBlock()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 872 bool IsKill = MO.isKill(); in MergeOpsUpdate() local
873 if (IsKill) in MergeOpsUpdate()
875 Regs.push_back(std::make_pair(Reg, IsKill)); in MergeOpsUpdate()
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