| /openbsd/src/gnu/llvm/llvm/lib/Target/XCore/ |
| D | XCoreSubtarget.h | 33 XCoreInstrInfo InstrInfo; variable
49 const XCoreInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
60 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARC/ |
| D | ARCSubtarget.h | 33 ARCInstrInfo InstrInfo; variable
51 const ARCInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
59 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| D | ARCSubtarget.cpp | 29 : ARCGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS), InstrInfo(*this), in ARCSubtarget()
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| /openbsd/src/gnu/llvm/llvm/utils/TableGen/GlobalISel/ |
| D | GIMatchTree.cpp | 396 GIMatchTreeInstrInfo *InstrInfo = Leaf.value().getInstrInfo(InstrID); in repartition() local
403 if (!InstrInfo) { in repartition()
421 if (PDep->getRequiredMI() == InstrInfo->getInstrNode() && in repartition()
444 if (PDep->getRequiredMI() == InstrInfo->getInstrNode() && in repartition()
517 GIMatchTreeInstrInfo *InstrInfo = Leaf.value().getInstrInfo(InstrID); in repartition() local
518 if (!InstrInfo) { in repartition()
569 GIMatchTreeInstrInfo *InstrInfo = Leaf.getInstrInfo(InstrID); in applyForPartition() local
571 if (!InstrInfo) in applyForPartition()
573 const GIMatchDagInstr *Instr = InstrInfo->getInstrNode(); in applyForPartition()
658 GIMatchTreeInstrInfo *InstrInfo = Leaf.value().getInstrInfo(InstrID); in repartition() local
[all …]
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| /openbsd/src/gnu/llvm/llvm/tools/llvm-exegesis/lib/ |
| D | LlvmState.cpp | 105 const MCInstrInfo &InstrInfo = getInstrInfo(); in createOpcodeNameToOpcodeIdxMapping() local
107 InstrInfo.getNumOpcodes()); in createOpcodeNameToOpcodeIdxMapping()
108 for (unsigned I = 0, E = InstrInfo.getNumOpcodes(); I < E; ++I) in createOpcodeNameToOpcodeIdxMapping()
109 (*Map)[InstrInfo.getName(I)] = I; in createOpcodeNameToOpcodeIdxMapping()
110 assert(Map->size() == InstrInfo.getNumOpcodes() && "Size prediction failed"); in createOpcodeNameToOpcodeIdxMapping()
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| D | Clustering.cpp | 189 const MCSubtargetInfo &SubtargetInfo, const MCInstrInfo &InstrInfo) { in clusterizeNaive() argument
194 const unsigned NumOpcodes = InstrInfo.getNumOpcodes(); in clusterizeNaive()
202 ResolvedSchedClass::resolveSchedClassId(SubtargetInfo, InstrInfo, MCI); in clusterizeNaive()
333 const MCSubtargetInfo *SubtargetInfo, const MCInstrInfo *InstrInfo) { in create() argument
346 if (InstrInfo) in create()
347 Clustering.stabilize(InstrInfo->getNumOpcodes()); in create()
349 if (!SubtargetInfo || !InstrInfo) in create()
352 Clustering.clusterizeNaive(*SubtargetInfo, *InstrInfo); in create()
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| D | MCInstrDescView.cpp | 106 Instruction::create(const MCInstrInfo &InstrInfo, in create() argument
109 const llvm::MCInstrDesc *const Description = &InstrInfo.get(Opcode); in create()
185 Description, InstrInfo.getName(Opcode), std::move(Operands), in create()
302 InstructionsCache::InstructionsCache(const MCInstrInfo &InstrInfo, in InstructionsCache() argument
304 : InstrInfo(InstrInfo), RATC(RATC), BVC() {} in InstructionsCache()
309 Found = Instruction::create(InstrInfo, RATC, BVC, Opcode); in getInstr()
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| D | MCInstrDescView.h | 109 create(const MCInstrInfo &InstrInfo, const RegisterAliasingTrackerCache &RATC,
174 InstructionsCache(const MCInstrInfo &InstrInfo,
181 const MCInstrInfo &InstrInfo;
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| D | SchedClassResolution.cpp | 242 const MCInstrInfo &InstrInfo, in ResolveVariantSchedClassId() argument
247 SchedClassId = STI.resolveVariantSchedClass(SchedClassId, &MCI, &InstrInfo, in ResolveVariantSchedClassId()
255 const MCInstrInfo &InstrInfo, in resolveSchedClassId() argument
257 unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass(); in resolveSchedClassId()
262 ResolveVariantSchedClassId(SubtargetInfo, InstrInfo, SchedClassId, MCI); in resolveSchedClassId()
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| D | Clustering.h | 35 const MCInstrInfo *InstrInfo = nullptr);
130 const MCInstrInfo &InstrInfo);
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Lanai/ |
| D | LanaiSubtarget.h | 48 const LanaiInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
55 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
68 LanaiInstrInfo InstrInfo; variable
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| /openbsd/src/gnu/llvm/llvm/lib/Target/VE/ |
| D | VESubtarget.h | 42 VEInstrInfo InstrInfo; variable
51 const VEInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
56 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/MSP430/ |
| D | MSP430Subtarget.h | 42 MSP430InstrInfo InstrInfo; variable
66 const MSP430InstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
68 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/BPF/ |
| D | BPFSubtarget.h | 33 BPFInstrInfo InstrInfo; variable
76 const BPFInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
87 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/NVPTX/ |
| D | NVPTXSubtarget.h | 42 NVPTXInstrInfo InstrInfo; variable
60 const NVPTXInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
62 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Sparc/ |
| D | SparcSubtarget.h | 55 SparcInstrInfo InstrInfo; variable
64 const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
69 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/SystemZ/ |
| D | SystemZSubtarget.h | 44 SystemZInstrInfo InstrInfo; variable
76 const SystemZInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
78 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| D | R600Subtarget.h | 32 R600InstrInfo InstrInfo;
50 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
61 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| D | AMDGPUSubtarget.cpp | 177 InstrInfo(initializeSubtargetDependencies(TT, GPU, FS)), in GCNSubtarget()
614 return InstrInfo.pseudoToMCOpcode(AMDGPU::V_MAD_F16_e64) != -1; in hasMadF16()
835 Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *I); in adjustSchedDependency()
845 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI); in adjustSchedDependency()
857 Dep.setLatency(InstrInfo.getSchedModel().computeOperandLatency( in adjustSchedDependency()
964 Mutations.push_back(std::make_unique<FillMFMAShadowMutation>(&InstrInfo)); in getPostRAMutations()
969 return EnablePowerSched ? std::make_unique<FillMFMAShadowMutation>(&InstrInfo) in createFillMFMAShadowMutation()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/AVR/ |
| D | AVRSubtarget.h | 42 const AVRInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
53 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
145 AVRInstrInfo InstrInfo; variable
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| /openbsd/src/gnu/llvm/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblySubtarget.h | 57 WebAssemblyInstrInfo InstrInfo; variable
80 return &InstrInfo; in getInstrInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/Mips/ |
| D | MipsSubtarget.h | 222 std::unique_ptr<const MipsInstrInfo> InstrInfo; variable
385 const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } in getInstrInfo()
390 return &InstrInfo->getRegisterInfo(); in getRegisterInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/RISCV/ |
| D | RISCVSubtarget.h | 60 RISCVInstrInfo InstrInfo; variable
86 const RISCVInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMSubtarget.h | 263 return InstrInfo.get(); in getInstrInfo()
275 return &InstrInfo->getRegisterInfo(); in getRegisterInfo()
288 std::unique_ptr<ARMBaseInstrInfo> InstrInfo; variable
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| /openbsd/src/gnu/llvm/llvm/lib/Target/PowerPC/ |
| D | PPCSubtarget.h | 105 PPCInstrInfo InstrInfo; variable
145 const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
|