Searched refs:Inp0 (Results 1 – 2 of 2) sorted by relevance
| /openbsd/src/gnu/llvm/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 3322 SDValue Inp0 = Op.getOperand(0); in LegalizeHvxResize() local
3323 MVT InpTy = ty(Inp0); in LegalizeHvxResize()
3337 SDValue W = appendUndef(Inp0, WInpTy, DAG); in LegalizeHvxResize()
3361 SDValue Inp0; // Optional first argument. in LowerHvxOperationWrapper() local
3363 Inp0 = Op.getOperand(0); in LowerHvxOperationWrapper()
3371 Subtarget.isHVXElementType(ty(Inp0))) { in LowerHvxOperationWrapper()
3376 if (shouldWidenToHvx(ty(Inp0), DAG)) { in LowerHvxOperationWrapper()
3406 if (ty(Op).getSizeInBits() != ty(Inp0).getSizeInBits()) { in LowerHvxOperationWrapper()
3427 SDValue Inp0; // Optional first argument. in ReplaceHvxNodeResults() local
3429 Inp0 = Op.getOperand(0); in ReplaceHvxNodeResults()
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| /openbsd/src/gnu/llvm/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 13231 SDValue Inp0 = in PerformVQDMULHCombine() local
13235 Inp0 = DAG.getNode(ARMISD::VECTOR_REG_CAST, DL, LegalVecVT, Inp0); in PerformVQDMULHCombine()
13237 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
13248 SDValue Inp0 = in PerformVQDMULHCombine() local
13254 SDValue VQDMULH = DAG.getNode(ARMISD::VQDMULH, DL, LegalVecVT, Inp0, Inp1); in PerformVQDMULHCombine()
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